Hitachi H8S/2199 Hardware Manual page 674

Drum System Digital Filter Control Register (DFIC)
Bit :
Initial value :
R/W :
Note: * Only 0 can be written
DFIC is an 8-bit read/write register that controls the status of the drum digital filter and operating
mode. Only a byte access is valid. If a word access is attempted, correct operation is not
guaranteed. DFIC is initialized to H'80 by a reset, and in standby mode and module stop mode.
Bit 7    Reserved: Cannot be modified and is always read as 1.
Bit 6    Drum System Range Over Flag (DROV): This flag is set to 1 when the result of a filter
computation exceeds 12 bits in width. To clear this flag, write 0 after reading 1.
Bit 6
DROV Description
0 Indicates that the filter computation result did not exceed 12 bits
1 Indicates that the filter computation result exceeded 12 bits
Bit 5    Drum Phase System Filter Computation Start Bit (DPHA): Starts or stops filter
processing for drum phase system.
Bit 5
DPHA Description
0 Phase system filter computations are disabled
Phase computation result (Y) is not added to Es (see figure 26.34)
1 Phase system filter computations are enabled
Rev. 1.0, 02/00, page 668 of 1141
7 6
DROV DPHA
—
1 0
— R/(W)* R/(W)
5 4
DZPON DZSON
0 0
R/W R/W
3 2
DSG2 DSG1
0 0
R/W R/W
1 0
DSG0
0 0
R/W
(Initial value)
(Initial value)