System Control Register (Syscr) - Hitachi H8S/2199 Hardware Manual

17.2.3

System Control Register (SYSCR)

Bit :
Initial value :
R/W :
Only bit 3 is described here. For details on functions not related to the watchdog timer, see
sections 3.2.2 and 6.2.1, System Control Register (SYSCR), and the descriptions of the relevant
modules.
Bit 3    External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a
reset can be generated by watchdog timer overflow in addition to external reset input. XRST is a
read-only bit. It is set to 1 by an external reset, and cleared to 0 by watchdog timer overflow.
Bit 3
XRST Description
0 Reset is generated by watchdog timer overflow
1 Reset is generated by external reset input
7 6
— — INTM1
0 0
— —
5 4
INTM0 XRST
0 0
R R/W
3 2
— —
1 0
R — —
Rev. 1.0, 02/00, page 353 of 1141
1 0
—
0 1
—
(Initial value)