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H'D098: DVCTL Control Register CTVC: Frequency Divider
Bit
:
7
CEX
Initial value
:
0
R/W
:
W
External sync signal edge select bit
0 Rising edge
1 Falling edge
DVCTL signal generation select bit
0 Generated by PB-CTL signal (Initial value)
1 Generated by external input signal
H'D099: CTL Frequency Division Register CTLR: Frequency Divider
Bit
:
CTL7
Initial value
:
R/W
:
Rev. 1.0, 02/00, page 1020 of 1141
6
5
—
CEG
0
1
—
W
(Initial value)
7
6
CTL6
CTL5
0
0
W
W
4
3
2
—
—
CFG
1
1
*
—
—
R
HSW flag
CFG flag
0 CFG level is low
1 CFG level is high
4
5
CTL4
CTL3
0
0
W
W
1
0
HSW
CTL
*
*
R
R
CTL flag
0 REC or PB-CTL level is low (Initial value)
1 REC or PB-CTL level is high
0 HSW level is low
(Initial value)
1 HSW level is high
(Initial value)
3
2
CTL2
CTL1
0
0
W
W
1
0
CTL0
0
0
W
W
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