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Hitachi H8S/2338 Series Hardware Manual

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H8S/2338 Series, H8S/2328 Series,

H8S/2318 Series

Hardware Manual

— Specifications Common to All Series —

ADE-602-171

Rev. 1.0

3/1/99

Hitachi, Ltd.

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Page 1 H8S/2338 Series, H8S/2328 Series, H8S/2318 Series Hardware Manual — Specifications Common to All Series — ADE-602-171 Rev. 1.0 3/1/99 Hitachi, Ltd.
Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 3 H8S/2318 Series Hardware Manual The H8S/2338 Series, H8S/2328 Series, H8S/2318 Series Hardware Manual describes the operation of on-chip functions common to the H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series, in particular, and gives a detailed description of the related registers. Information specific...
Page 4 In addition, an on-chip DMA controller (DMAC) and data transfer controller (DTC) are provided, enabling high-speed data transfer without CPU intervention. Use of the H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series enables easy implementation of compact, high-performance systems capable of processing large volumes of data.
Page 5: Table Of Contents
Contents Section 1 Overview ......................Overview..........................Section 2 Exception Handling ..................Overview..........................2.1.1 Exception Handling Types and Priority ............... 2.1.2 Exception Handling Operation ................2.1.3 Exception Vector Table..................Reset ..........................10 2.2.1 Overview ......................10 2.2.2 Reset Sequence..................... 2.2.3 Interrupts after Reset .................... 11 2.2.4 State of On-Chip Supporting Modules after Reset Release .........
Page 6 3.4.4 Interrupt Exception Handling Sequence .............. 37 3.4.5 Interrupt Response Times..................Usage Notes ........................3.5.1 Contention between Interrupt Generation and Disabling........3.5.2 Instructions that Disable Interrupts ..............41 3.5.3 Times when Interrupts are Disabled..............3.5.4 Interrupts during Execution of EEPMOV Instruction.......... 41 DTC and DMAC Activation by Interrupt................
Page 7 4.5.3 Address Multiplexing ................... 4.5.4 Data Bus ....................... 4.5.5 Pins Used for DRAM Interface ................84 4.5.6 Basic Timing ......................85 4.5.7 Precharge State Control..................86 4.5.8 Wait Control ......................4.5.9 Byte Access Control ..................... 4.5.10 Burst Operation ....................91 4.5.11 Refresh Control ....................
Page 8 5.2.3 Execute Transfer Count Register (ETCR)............121 5.2.4 DMA Control Register (DMACR)............... 122 5.2.5 DMA Band Control Register (DMABCR)............126 Register Descriptions (2) (Full Address Mode) ..............131 5.3.1 Memory Address Register (MAR) ............... 131 5.3.2 I/O Address Register (IOAR)................131 5.3.3 Execute Transfer Count Register (ETCR)............
Page 9 6.2.3 DTC Source Address Register (SAR) ..............205 6.2.4 DTC Destination Address Register (DAR) ............205 6.2.5 DTC Transfer Count Register A (CRA) .............. 205 6.2.6 DTC Transfer Count Register B (CRB) ............... 206 6.2.7 DTC Enable Registers (DTCER) ................. 206 6.2.8 DTC Vector Register (DTVECR)................
Page 10 Operation ........................... 273 7.4.1 Overview ......................273 7.4.2 Basic Functions ....................274 7.4.3 Synchronous Operation ..................280 7.4.4 Buffer Operation ....................282 7.4.5 Cascaded Operation....................286 7.4.6 PWM Modes ......................288 7.4.7 Phase Counting Mode ..................293 Interrupts..........................300 7.5.1 Interrupt Sources and Priorities................
Page 11 Section 9 8-Bit Timers ..................... 347 Overview..........................347 9.1.1 Features ........................ 347 9.1.2 Block Diagram...................... 348 9.1.3 Pin Configuration ....................349 9.1.4 Register Configuration ..................349 Register Descriptions......................350 9.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1)............350 9.2.2 Time Constant Registers A0 and A1 (TCORA0, TCORA1) ....... 350 9.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1)........
Page 12 10.3.1 Operation in Watchdog Timer Mode ..............379 10.3.2 Operation in Interval Timer Mode ............... 381 10.3.3 Timing of Overflow Flag (OVF) Setting.............. 381 10.3.4 Timing of Watchdog Timer Overflow Flag (WOVF) Setting......382 10.4 Interrupts..........................382 10.5 Usage Notes ........................382 10.5.1 Contention between Timer Counter (TCNT) Write and Increment .....
Page 13 12.2 Register Descriptions......................457 12.2.1 Smart Card Mode Register (SCMR) ..............457 12.2.2 Serial Status Register (SSR)................. 458 12.2.3 Serial Mode Register (SMR)................459 12.2.4 Serial Control Register (SCR)................461 12.3 Operation ........................... 462 12.3.1 Overview ......................462 12.3.2 Pin Connections....................462 12.3.3 Data Format......................
Page 14 14.2.1 A/D Data Registers A to D (ADDRA to ADDRD)..........512 14.2.2 A/D Control/Status Register (ADCSR)..............513 14.2.3 A/D Control Register (ADCR)................515 14.2.4 Module Stop Control Register (MSTPCR) ............516 14.3 Interface to Bus Master...................... 517 14.4 Operation ........................... 518 14.4.1 Single Mode (SCAN = 0) ..................
Page 15 17.4.1 Features ........................ 544 17.4.2 Overview ......................545 17.4.3 Flash Memory Operating Modes................546 17.4.4 On-Board Programming Modes ................547 17.4.5 Flash Memory Emulation in RAM............... 549 17.4.6 Differences between Boot Mode and User Program Mode........550 17.4.7 Block Configuration ..................... 551 17.4.8 Pin Configuration ....................
Page 16 17.12 Flash Memory Programming and Erasing Precautions ............. 593 Section 18 Clock Pulse Generator .................. 599 18.1 Overview..........................599 18.1.1 Block Diagram...................... 599 18.1.2 Register Configuration ..................600 18.2 Register Descriptions......................600 18.2.1 System Clock Control Register (SCKCR) ............600 18.3 Oscillator..........................
Page 17 Bus States During Instruction Execution ................680 Condition Code Modification.................... 694 Appendix B Internal I/O Registers ................700 Addresses........................... 700 xiii...
Page 18: Overview
CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching is thus speeded up, and processing speed increased. The features of the H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series are shown in table 1-1.
Page 19 Table 1-1 Overview Item Specification • General-register machine  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control  Maximum clock rate: 20 MHz (25 MHz version in planning stage) ...
Page 20 Table 1-1 Overview (cont) Item Specification • 6-channel 16-bit timer 16-bit timer-pulse • unit (TPU) Pulse I/O processing capability for up to 16 pins • Automatic 2-phase encoder count capability • Maximum 16-bit pulse output possible with TPU as time base Programmable •...
Page 21 Table 1-1 Overview (cont) Item Specification • Eight MCU operating modes (F-ZTAT version) Operating modes External Data Bus Operating On-Chip Initial Maximum Mode Mode Description Value Value — — — — — Advanced On-chip ROM disabled Disabled 16 bits 16 bits expansion mode 8 bits 16 bits...
Page 22 Table 1-1 Overview (cont) Item Specification • Four MCU operating modes (ROMless and mask ROM versions) Operating modes External Data Bus Operating On-Chip Initial Maximum Mode Mode Description Value Value — — — — — Advanced On-chip ROM disabled Disabled 16 bits 16 bits expansion mode On-chip ROM disabled...
Page 23: Exception Handling
Section 2 Exception Handling Overview 2.1.1 Exception Handling Types and Priority As table 2-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 2-1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Page 24: Exception Handling Operation
2.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extend register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3.
Page 25 Table 2-2 Exception Vector Table Vector Address* Exception Source Vector Number Advanced Mode Power-on reset H'0000 to H'0003 Reserved H'0004 to H'0007 Reserved for system use H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 Trace H'0014 to H'0017 Reserved for system use H'0018 to H'001B External interrupt H'001C to H'001F...
Page 26: Reset
A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules.
Page 27: Interrupts After Reset
Internal Prefetch of first Vector fetch processing program instruction ø Address bus High HWR, LWR to D (1), (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) (2), (4) Start address (contents of reset exception vector address) Start address ((5) = (2), (4)) First program instruction Note: * 3 program wait states are inserted.
Page 28: Traces
Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 3, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction.
Page 29: Interrupts
Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 52 internal sources in the on-chip supporting modules. Figure 2-3 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), refresh timer, 16-bit timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI), data transfer controller (DTC), DMA controller (DMAC), and A/D converter.
Page 30: Trap Instruction
Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code.
Page 31: Notes On Use Of The Stack
Notes on Use of the Stack When accessing word data or longword data, the H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series assume that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even.
Page 32: Interrupt Controller
3.1.1 Features The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series control interrupts by means of an interrupt controller. The interrupt controller has the following features. This chapter assumes the maximum number of interrupt sources available in these series—nine external interrupts and 52 internal interrupts.
Page 33: Block Diagram
3.1.2 Block Diagram A block diagram of the interrupt controller is shown in Figure 3-1. INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit Interrupt request IRQ input unit IRQ input Vector number Priority ISCR determination Internal interrupt request I2 to I0 SWDTEND to TEI Interrupt controller Legend...
Page 34: Pin Configuration
3.1.3 Pin Configuration Table 3-1 summarizes the pins of the interrupt controller. Table 3-1 Interrupt Controller Pins Name Symbol Function Nonmaskable interrupt Input Nonmaskable external interrupt; rising or falling edge can be selected IRQ7 to IRQ0 Input External interrupt Maskable external interrupts; rising, falling, or requests 7 to 0 both edges, or level sensing, can be selected 3.1.4...
Page 35 Register Descriptions 3.2.1 System Control Register (SYSCR) — — INTM1 INTM0 NMIEG LWROD IRQPAS RAME Initial value : — SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see the MCU Operating Modes section in the reference manual for the relevant model.
Page 36: Interrupt Priority Registers A To K (Ipra To Iprk)
3.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 Initial value : — — The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between IPR settings and interrupt sources is shown in table 3-3.
Page 37: Irq Enable Register (Ier)
As shown in table 3-3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt.
Page 38: Irq Sense Control Registers H And L (Iscrh, Iscrl)
3.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : ISCR (composed of ISCRH and ISCRL) is a 16-bit readable/writable register that selects rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0.
Page 39: Irq Status Register (Isr)
3.2.5 IRQ Status Register (ISR) IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests.
Page 40: Interrupt Sources
There are nine external interrupts: NMI and IRQ7 to IRQ0. NMI and IRQ7 to IRQ0 can be used to restore the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip from software standby mode. (IRQ7 to IRQ3 can be designated for use as software standby mode clearing sources by setting the IRQ37S bit in SBYCR to 1.)
Page 41: Internal Interrupts
Figure 3-3 shows the timing of setting IRQnF. ø IRQn input pin IRQnF Figure 3-3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output.
Page 42 Table 3-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Vector Vector Interrupt Source Source Number Address* Priority External H'001C High IRQ0 H'0040 IPRA6 to 4 IRQ1 H'0044 IPRA2 to 0 IRQ2 H'0048 IPRB6 to 4 IRQ3 H'004C IRQ4 H'0050 IPRB2 to 0...
Page 43 Table 3-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities (cont) Origin of Interrupt Vector Vector Interrupt Source Source Number Address* Priority TGI1A (TGR1A input capture/ H'00A0 IPRF2 to 0 High compare match) channel 1 TGI1B (TGR1B input capture/ H'00A4 compare match) TCI1V (overflow 1) H'00A8 TCI1U (underflow 1)
Page 44 Table 3-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities (cont) Origin of Interrupt Vector Vector Interrupt Source Source Number Address* Priority CMIA0 (compare match A0) 8-bit timer H'0100 IPRI6 to 4 High channel 0 CMIB0 (compare match B0) H'0104 OVI0 (overflow 0) H'0108 Reserved —...
Page 45: Interrupt Operation
3.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt.
Page 46 Figure 3-4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 Interrupt acceptance control Default priority Interrupt source Vector number determination 8-level mask control I2 to I0 Interrupt control mode 2 Figure 3-4 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR.
Page 47 8-Level Control: In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level.
Page 48: Interrupt Control Mode 0
3.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1.
Page 49 Program execution state Interrupt generated? NMI? I = 0? Hold pending IRQ0? IRQ1? TEI2? Save PC and CCR I ← 1 Read vector address Branch to interrupt handling routine Figure 3-5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0...
Page 50 3.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 3-6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller.
Page 51: Interrupt Control Mode 2
Program execution state Interrupt generated? NMI? Level 7 interrupt? Level 6 interrupt? Mask level 6 Level 1 interrupt? or below? Mask level 5 or below? Mask level 0? Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine...
Page 52: Interrupt Exception Handling Sequence
3.4.4 Interrupt Exception Handling Sequence Figure 3-7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory.
Page 53 Figure 3-7 Interrupt Exception Handling...
Page 54: Interrupt Response Times
3.4.5 Interrupt Response Times The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series are capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing.
Page 55: Usage Notes
Usage Notes 3.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction.
Page 56: Instructions That Disable Interrupts
3.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends.
Page 57: Dtc And Dmac Activation By Interrupt
DTC and DMAC Activation by Interrupt 3.6.1 Overview The DTC and DMAC can be activated by an interrupt. In this case, the following options are available. Some models do not have an on-chip DMAC; see the reference manual for the relevant model.
Page 58: Operation
3.6.3 Operation The interrupt controller has three main functions in DTC and DMAC control. Selection of Interrupt Source: With the DMAC, the activation source is input directly to each channel. The activation source for each DMAC channel is selected with bits DTF3 to DTF0 in DMACR.
Page 59 Table 3-11 Interrupt Source Selection and Clearing Control Settings DMAC Interrupt Source Selection/Clearing Control DTCE DISEL DMAC Legend : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used.
Page 60: Bus Controller
Section 4 Bus Controller Overview The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series have a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily.
Page 61 • Idle cycle insertion  An idle cycle can be inserted in case of an external read cycle between different areas  An idle cycle can be inserted when an external read cycle is immediately followed by an external write cycle •...
Page 62: Block Diagram
4.1.2 Block Diagram Figure 4-1 shows a block diagram of the bus controller. CS0 to CS7 Internal Area decoder address bus ABWCR External bus control signals ASTCR BCRH BCRL BREQ BACK Internal control BREQO controller signals Bus mode signal Wait WAIT controller WCRH...
Page 63: Pin Configuration
4.1.3 Pin Configuration Table 4-1 summarizes the pins of the bus controller. The pins used for output of the various signals differ from model to model; see the reference manual for the relevant model for details. Table 4-1 Bus Controller Pins Name Symbol I/O Function...
Page 64: Register Configuration
Table 4-1 Bus Controller Pins (cont) Name Symbol I/O Function Upper column address strobe Output 2-CAS DRAM upper column address strobe signal. LCAS Lower column strobe Output DRAM lower column address strobe signal. WAIT Wait Input Wait request signal when accessing external 3-state access space.
Page 65: Register Descriptions
Register Descriptions 4.2.1 Bus Width Control Register (ABWCR) ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Modes 5 to 7 Initial value : Mode 4 Initial value : ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access.
Page 66: Access State Control Register (Astcr)
4.2.2 Access State Control Register (ASTCR) AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 Initial value : ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR.
Page 67: Wait Control Registers H And L (Wcrh, Wcrl)
4.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode.
Page 68 Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 Bit 2 Description Program wait not inserted when external space area 5 is accessed...
Page 69 WCRL Initial value : Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.
Page 70: Bus Control Register H (Bcrh)
Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 Bit 2 Description Program wait not inserted when external space area 1 is accessed...
Page 71 Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 Description Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas (Initial value) Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted...
Page 72 Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description Max. 4 words in burst access (Initial value) Max. 8 words in burst access Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): These bits select the memory interface for areas 2 to 5 in advanced mode.
Page 73 Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release. Bit 7 BRLE Description External bus release is disabled. BREQ, BACK, and BREQO pins can be used as I/O ports (Initial value) External bus release is enabled Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal (BREQ) in the external bus release state, when an internal bus master performs an external space access, or when a refresh request is generated.
Page 74 Bit 4—Reserved Bit 3—DACK Timing Select (DDS): Selects the DMAC single address transfer bus timing for the DRAM interface. Bit 3 Description When DMAC single address transfer is performed in DRAM space, full access is always executed DACK signal goes low from T or T cycle Burst access is possible when DMAC single address transfer is performed in DRAM...
Page 75: Memory Control Register (Mcr)
4.2.6 Memory Control Register (MCR) RCDM – MXC1 MXC0 RLW1 RLW0 Initial value : MCR is an 8-bit readable/writable register that selects the DRAM strobe control method, number of precharge cycles, access mode, address multiplexing shift size, and the number of wait states inserted during refreshing, when areas 2 to 5 are designated as DRAM interface areas.
Page 76 Bit 4—Reserved Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the shift to the lower half of the row address in row address/column address multiplexing for the DRAM interface. In burst operation on the DRAM interface, these bits also select the row address to be used for comparison.
Page 77: Dram Control Register (Dramcr)
4.2.7 DRAM Control Register (DRAMCR) RFSHE RMODE CMIE CKS2 CKS1 CKS0 Initial value : DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh counter clock, and controls the refresh timer. DRAMCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Page 78: Refresh Timer Counter (Rtcnt)
Bit 4 Description [Clearing condition] Cleared by reading the CMF flag when CMF = 1, then writing 0 to the CMF flag (Initial value) [Setting condition] Set when RTCNT = RTCOR Bit 3—Compare Match Interrupt Enable (CMIE): Enables or disables interrupt requests (CMI) by the CMF flag when the CMF flag in DRAMCR is set to 1.
Page 79: Refresh Time Constant Register (Rtcor)
RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits CKS2 to CKS0 in DRAMCR. When RTCNT matches RTCOR (compare match), the CMF flag in DRAMCR is set to 1 and RTCNT is cleared to H'00. If the RFSHE bit in DRAMCR is set to 1 at this time, a refresh cycle is started.
Page 80 H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 Mbytes) H'DFFFFF H'E00000 Area 7...
Page 81: Bus Specifications
4.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller.
Page 82: Memory Interfaces
4.3.3 Memory Interfaces The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; and a burst ROM interface that allows direct connection of burst ROM.
Page 83: Advanced Mode
4.3.4 Advanced Mode The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (4.4, 4.5, and 4.7) should be referred to for further details.
Page 84: Chip Select Signals
4.3.5 Chip Select Signals The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. Figure 4-3 shows an example of CSn (n = 0 to 7) output timing.
Page 85: Basic Bus Interface
Basic Bus Interface 4.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 4- 4.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D to D...
Page 86 16-Bit Access Space: Figure 4-5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D to D ) and lower data bus (D to D ) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions.
Page 87: Valid Strobes
4.4.3 Valid Strobes Table 4-4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
Page 88: Basic Timing
4.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 4-6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D to D ) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle ø...
Page 89 8-Bit 3-State Access Space: Figure 4-7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D to D ) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle ø...
Page 90 16-Bit 2-State Access Space: Figures 4-8 to 4-10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D to D ) of the data bus is used for the even address, and the lower half (D to D ) for the odd address.
Page 91 Bus cycle ø Address bus to D Read Invalid to D Valid High Write High impedance to D to D Valid Note: n = 0 to 7 Figure 4-9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)
Page 92 Bus cycle ø Address bus to D Read Valid to D Valid Write to D Valid to D Valid Note: n = 0 to 7 Figure 4-10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)
Page 93 16-Bit 3-State Access Space: Figures 4-11 to 4-13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D to D ) of the data bus is used for the even address, and the lower half (D to D ) for the odd address.
Page 94 Bus cycle ø Address bus to D Invalid Read to D Valid High Write High impedance to D to D Valid Note: n = 0 to 7 Figure 4-12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access)
Page 95 Bus cycle ø Address bus to D Valid Read to D Valid Write to D Valid to D Valid Note: n = 0 to 7 Figure 4-13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)
Page 96: Wait Control
4.4.5 Wait Control When accessing external space, the H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series can extend the bus cycle by inserting one or more wait states (T ). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin.
Page 97 Figure 4-14 shows an example of wait state insertion timing. By program wait By WAIT pin ø WAIT Address bus Read Data bus Read data HWR, LWR Write Data bus Write data Note: indicates the timing of WAIT pin sampling. Figure 4-14 Example of Wait State Insertion Timing The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled.
Page 98: Dram Interface
4.5.1 Overview When the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip is in advanced mode, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the chip. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in BCRH.
Page 99: Data Bus
4.5.4 Data Bus If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM space.
Page 100: Basic Timing
4.5.6 Basic Timing Figure 4-15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4 states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion, and do not affect the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states cannot be inserted in the DRAM access cycle.
Page 101: Precharge State Control
4.5.7 Precharge State Control When DRAM is accessed, an RAS precharging time must be secured. With the H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series, one T state is always inserted when DRAM space is accessed. This can be changed to two T states by setting the TPC bit in MCR to 1.
Page 102: Wait Control
4.5.8 Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to 3 wait states can be inserted automatically between the T state and T state, according to the settings of WCRH and WCRL.
Page 103 By program wait By WAIT pin ø WAIT * Address bus C Sn (RAS) Read Data bus Read data Write Data bus Write data indicates the timing of WAIT pin sampling. Notes: n = 2 to 5 The pin that can be used for wait input, and the setting conditions, differ from model to model; see the reference manual for the relevant model for details.
Page 104: Byte Access Control
4.5.9 Byte Access Control When DRAM with a ×16 configuration is connected, the 2-CAS system can be used for the control signals required for byte access. Figure 4-18 shows the control timing in the 2-CAS system, and figure 4-19 shows an example of 2-CAS type DRAM connection.
Page 105 H8S/2338 Series, H8S/2328 Series, 2-CAS type 4-Mbit DRAM 256-kbyte × 16-bit configuration or H8S/2318 Series (Address shift size set to 9 bits) 9-bit column address CS (RAS) UCAS LCAS LCAS HWR (WE) Row address input: A to A Column address...
Page 106: Burst Operation
4.5.10 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output.
Page 107 RAS Down Mode and RAS Up Mode: Even when burst operation is selected, it may happen that access to DRAM space is not continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low during the access to the other space, burst operation can be resumed when the same row address in DRAM space is accessed again.
Page 108 • RAS up mode To select RAS up mode, clear the RCDM bit in MCR to 0. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 4-22 shows an example of the timing in RAS up mode.
Page 109: Refresh Control
4.5.11 Refresh Control The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series are provided with a DRAM refresh control function. Either of two refreshing methods can be selected: CAS-before-RAS (CBR) refreshing, or self-refreshing. CAS-before-RAS (CBR) Refreshing: To select CBR refreshing, set the RFSHE bit in DRAMCR to 1, and clear the RMODE bit to 0.
Page 110 ø RTCNT H'00 RTCOR Refresh request signal and CMF bit setting signal Figure 4-24 Compare Match Timing ø CS (RAS) CAS, LCAS Figure 4-25 CBR Refresh Timing When the RCW bit is set to 1, RAS signal output is delayed by one cycle. The width of the RAS signal should be adjusted with bits RLW1 and RLW0.
Page 111 Figure 4-26 shows the timing when the RCW bit is set to 1. ø CSn (RAS) CAS, LCAS Figure 4-26 CBR Refresh Timing (When RCW = 1, RLW1 = 0, RLW0 = 1) Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode.
Page 112: Dmac Single Address Mode And Dram Interface
DMAC Single Address Mode and DRAM Interface When burst mode is selected with the DRAM interface, the DACK output timing can be selected with the DDS bit. When DRAM space is accessed in DMAC single address mode at the same time, this bit selects whether or not burst access is to be performed.
Page 113: When Dds = 0
4.6.2 When DDS = 0 When DRAM space is accessed in DMAC single address mode, full access (normal access) is always performed. The DACK output goes low from the T state in the case of the DRAM interface. In modes other than DMAC single address mode, burst access can be used when accessing DRAM space.
Page 114: Burst Rom Interface
4.7.1 Overview With the H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed.
Page 115 Full access Burst access ø Only lower address changed Address bus Data bus Read data Read data Read data Figure 4-30 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)
Page 116: Wait Control
Full access Burst access ø Only lower address changed Address bus Data bus Read data Read data Read data Figure 4-30 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 4.7.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface.
Page 117: Idle Cycle
Idle Cycle 4.8.1 Operation When the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip accesses external space, it can insert a 1-state idle cycle (T ) between bus cycles in the following two cases: (1) when read accesses in different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle.
Page 118 Write after Read: If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 4-32 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
Page 119 Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 4.33. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal.
Page 120 External read DRAM space read ø Address bus Data bus Figure 4-34 Example of DRAM Access after External Read DRAM space read External read DRAM space read EXTAL Address CAS, LCAS Data bus Idle cycle Figure 4-35 (a) Example of Idle Cycle Operation in RAS Down Mode (ICIS1 = 1)
Page 121: Pin States In Idle Cycle
DRAM space read External read DRAM space write EXTAL Address CAS, LCAS Data bus Idle cycle Figure 4-35 (b) Example of Idle Cycle Operation in RAS Down Mode (ICIS0 = 1) 4.8.2 Pin States in Idle Cycle Table 4-8 shows the pin states in an idle cycle. Table 4-8 Pin States in Idle Cycle Pins...
Page 122: Write Data Buffer Function
Write Data Buffer Function The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series have a write data buffer function in the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit in BCRL to 1.
Page 123: Bus Release
4.10.1 Overview The H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access.
Page 124: Pin States In External Bus Released State
As a refresh and an external access by an internal bus master can be executed simultaneously, there is no relative order of priority for these two operations. 4.10.3 Pin States in External Bus Released State Table 4-9 shows the pin states in the external bus released state. Table 4-9 Pin States in Bus Released State Pins...
Page 125: Transition Timing
4.10.4 Transition Timing Figure 4-37 shows the timing for transition to the bus released state. cycle CPU cycle External bus released state ø High impedance Address bus Address High impedance Data bus High impedance High impedance High impedance HWR, LWR BREQ BACK BREQO *...
Page 126: Usage Note
Bus Arbitration 4.11.1 Overview The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series have a bus arbiter that arbitrates bus master operations. There are three bus masters, the CPU, DTC, and DMAC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal.
Page 127: Bus Transfer Timing
4.12 Resets and the Bus Controller In a reset, the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip, including the bus controller, enters the reset state at that point, and any executing bus cycle is discontinued.
Page 128: Dma Controller
Section 5 DMA Controller Overview The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series have a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels. 5.1.1 Features The features of the DMAC are listed below.
Page 129: Block Diagram
• Module stop mode can be set  The initial setting enables DMAC registers to be accessed. DMAC operation is halted by setting module stop mode 5.1.2 Block Diagram A block diagram of the DMAC is shown in figure 5-1. Internal address bus Internal interrupts TGI0A...
Page 130: Overview Of Functions
5.1.3 Overview of Functions Tables 5-1 (1) and (2) summarize DMAC functions in short address mode and full address mode, respectively. Table 5-1 (1) Overview of DMAC Functions (Short Address Mode) Address Register Bit Length Transfer Mode Transfer Source Source Destination •...
Page 131 Table 5-1 (2) Overview of DMAC Functions (Full Address Mode) Address Register Bit Length Transfer Mode Transfer Source Source Destination • • Normal mode Auto-request Auto-request  Transfer request retained internally  Transfers continue for the specified number of times (1 to 65536) ...
Page 132: Pin Configuration
5.1.4 Pin Configuration Table 5-2 summarizes the DMAC pins. The pins used for output of the various signals differ from model to model; see the reference manual for the relevant model for details. In short address mode, external request transfer, single address transfer, and transfer end output are not performed for channel A.
Page 133: Register Configuration
5.1.5 Register Configuration Table 5-3 summarizes the DMAC registers. Table 5-3 DMAC Registers Initial Channel Name Abbreviation R/W Value Address* Bus Width Memory address register 0A MAR0A Undefined H'FEE0 16 bits I/O address register 0A IOAR0A Undefined H'FEE4 16 bits Transfer count register 0A ETCR0A Undefined H'FEE6...
Page 134: Register Descriptions (1) (Short Address Mode)
Register Descriptions (1) (Short Address Mode) Short address mode transfer can be performed for channels A and B independently. Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to 0, as shown in table 5-4. Short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits FAE1 and FAE0.
Page 135: Memory Address Registers (Mar)
5.2.1 Memory Address Registers (MAR) — — — — — — — — Initial value : — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined MAR is a 32-bit readable/writable register that specifies the transfer source address or destination address.
Page 136: I/O Address Register (Ioar)
5.2.2 I/O Address Register (IOAR) IOAR Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source address or destination address.
Page 137: Dma Control Register (Dmacr)
Repeat Mode Transfer Number Storage (ETCRH) Initial value : Transfer Counter (ETCRL) Initial value : *: Undefined In repeat mode, ETCR functions as transfer counter ETCRL (with a count range of 1 to 256) and transfer number storage register ETCRH. ETCRL is decremented by 1 each time a transfer is performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH.
Page 138 Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 7 DTSZ Description Byte-size transfer (Initial value) Word-size transfer Bit 6—Data Transfer Increment/Decrement (DTID): Selects incrementing or decrementing of MAR after every data transfer in sequential mode or repeat mode. In idle mode, MAR is neither incremented nor decremented.
Page 139 DMABCR Bit 4 DTDIR Description Transfer with MAR as source address and IOAR as destination address (Initial value) Transfer with IOAR as source address and MAR as destination address Transfer with MAR as source address and DACK pin as write strobe Transfer with DACK pin as read strobe and MAR as destination address Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source).
Page 140 Channel B Bit 3 Bit 2 Bit 1 Bit 0 DTF3 DTF2 DTF1 DTF0 Description — (Initial value) Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* Activated by DREQ pin low-level input Activated by SCI channel 0 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt Activated by SCI channel 1 reception complete interrupt...
Page 141: Dma Band Control Register (Dmabcr)
5.2.5 DMA Band Control Register (DMABCR) DMABCRH FAE1 FAE0 SAE1 SAE0 DTA1B DTA1A DTA0B DTA0A Initial value : DMABCRL DTE1B DTE1A DTE0B DTE0A DTIE1B DTIE1A DTIE0B DTIE0A Initial value : DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel.
Page 142 Bit 13—Single Address Enable 1 (SAE1): Specifies whether channel 1B is to be used for transfer in dual address mode or single address mode. This bit is invalid in full address mode. Bit 13 SAE1 Description Transfer in dual address mode (Initial value) Transfer in single address mode Bit 12—Single Address Enable 0 (SAE0): Specifies whether channel 0B is to be used for...
Page 143 Bit 11 DTA1B Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 10—Data Transfer Acknowledge 1A (DTA1A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1A data transfer factor setting.
Page 144 The conditions for the DTE bit being cleared to 0 are as follows: • When initialization is performed • When the specified number of transfers have been completed in a transfer mode other than repeat mode • When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason When DTE = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the data transfer factor setting.
Page 145 Bits 3 to 0—Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
Page 146: Register Descriptions (2) (Full Address Mode)
Register Descriptions (2) (Full Address Mode) Full address mode transfer is performed with channels A and B together. For details of full address mode setting, see table 5-4. 5.3.1 Memory Address Register (MAR) — — — — — — — —...
Page 147: Execute Transfer Count Register (Etcr)
5.3.3 Execute Transfer Count Register (ETCR) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The function of this register is different in normal mode and in block transfer mode. ETCR is not initialized by a reset or in standby mode. Normal Mode ETCRA Transfer Counter...
Page 148: Dma Control Register (Dmacr)
ETCRB Block Transfer Counter Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH holds the block size.
Page 149 Bit 15—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 15 DTSZ Description Byte-size transfer (Initial value) Word-size transfer Bit 14—Source Address Increment/Decrement (SAID) Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed.
Page 150 Bits 10 to 7—Reserved: Can be read or written to. Bit 6—Destination Address Increment/Decrement (DAID) Bit 5—Destination Address Increment/Decrement Enable (DAIDE): These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed. Bit 6 Bit 5 DAID...
Page 151 • Block Transfer Mode Bit 3 Bit 2 Bit 1 Bit 0 DTF3 DTF2 DTF1 DTF0 Description — (Initial value) Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* Activated by DREQ pin low-level input Activated by SCI channel 0 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt...
Page 152: Dma Band Control Register (Dmabcr)
5.3.5 DMA Band Control Register (DMABCR) DMABCRH FAE1 FAE0 — — DTA1 — DTA0 — Initial value : DMABCRL DTME1 DTE1 DTME0 DTE0 DTIE1B DTIE1A DTIE0B DTIE0A Initial value : DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel.
Page 153 Bits 13 and 12—Reserved: Can be read or written to. Bits 11 and 9—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer.
Page 154 Bits 10 and 8—Reserved: Can be read or written to. Bits 7 and 5—Data Transfer Master Enable (DTME): Together with the DTE bit, these bits control enabling or disabling of data transfer on the relevant channel. When both the DTME bit and the DTE bit are set to 1, transfer is enabled for the channel.
Page 155 Bits 6 and 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU.
Page 156 Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1 transfer break interrupt. Bit 3 DTIE1B Description Transfer break interrupt disabled (Initial value) Transfer break interrupt enabled Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0 transfer break interrupt.
Page 157: Register Descriptions (3)
Register Descriptions (3) 5.4.1 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions so that specific bits of DMACR for the specific channel, and also DMATCR and DMABCR, can be changed to prevent inadvertent rewriting of registers other than those for the channel concerned.
Page 158 — — — — WE1B WE1A WE0B WE0A Initial value : — — — — DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to DMACR, DMABCR, and DMATCR by the DTC. DMAWER is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 to 4—Reserved: Read-only bits, always read as 0.
Page 159: Dma Terminal Control Register (Dmatcr)
Bit 0—Write Enable 0A (WE0A): Enables or disables writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR, by the DTC. Bit 0 WE0A Description Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled (Initial value) Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the...
Page 160: Module Stop Control Register (Mstpcr)
Bit 4—Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 (TEND0) output. Bit 4 TEE0 Description TEND0 pin output disabled (Initial value) TEND0 pin output enabled The TEND pins are assigned only to channel B in short address mode. The transfer end signal indicates the transfer cycle in which the transfer counter reached 0, regardless of the transfer source.
Page 161: Operation
Operation 5.5.1 Transfer Modes Table 5-5 lists the DMAC modes. Table 5-5 DMAC Transfer Modes Transfer Mode Transfer Source Remarks • • Short Dual (1) Sequential TPU channel 0 to 5 Up to 4 channels can address address mode compare match/input operate independently mode mode...
Page 162 Operation in each mode is summarized below. Sequential Mode: In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed.
Page 163: Sequential Mode
Block Transfer Mode: In response to a single transfer request, a block transfer of the specified block size is carried out. This is repeated the specified number of times, once each time there is a transfer request. At the end of each single block transfer, one address is restored to its original setting.
Page 164 MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.
Page 165 Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only. Figure 5-4 shows an example of the setting procedure for sequential mode.
Page 166: Idle Mode
5.5.3 Idle Mode Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR.
Page 167 Figure 5-5 illustrates operation in idle mode. Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Figure 5-5 Operation in Idle Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends.
Page 168 Figure 5-6 shows an example of the setting procedure for idle mode. [1] Set each bit in DMABCRH. Idle mode setting • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit.
Page 169: Repeat Mode
5.5.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR.
Page 170 MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF.
Page 171 Figure 5-7 illustrates operation in repeat mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Legend Address T = L DTID DTSZ Address B = L + (–1) · (2 · (N–1)) Where : L = Value set in MAR Address B N = Value set in ETCR...
Page 172 Figure 5-8 shows an example of the setting procedure for repeat mode. [1] Set each bit in DMABCRH. Repeat mode setting • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit.
Page 173: Single Address Mode
5.5.5 Single Address Mode Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCR to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK).
Page 174 Figure 5-9 illustrates operation in single address mode (when sequential mode is specified). DACK Address T Transfer 1 byte or word transfer performed in response to 1 transfer request Legend Address T = L DTID DTSZ Address B = L + (–1) ·...
Page 175 Figure 5-10 shows an example of the setting procedure for single address mode (when sequential mode is specified). [1] Set each bit in DMABCRH. Single address • Clear the FAE bit to 0 to select short address mode setting mode. •...
Page 176: Normal Mode
5.5.6 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRA.
Page 177 Figure 5-11 illustrates operation in normal mode. Address T Transfer Address T Address B Address B Legend Address Address SAID DTSZ Address + SAIDE · (–1) · (2 · (N–1)) DAID DTSZ Address + DAIDE · (–1) · (2 · (N–1)) Where : = Value set in MARA = Value set in MARB...
Page 178 For setting details, see section 5.3.4, DMA Control Register (DMACR). Figure 5-12 shows an example of the setting procedure for normal mode. [1] Set each bit in DMABCRH. Normal mode setting • Set the FAE bit to 1 to select full address mode.
Page 179 5.5.7 Block Transfer Mode In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times.
Page 180 Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in DMACRA. To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL, and N in ETCRB.
Page 181 Figure 5-14 illustrates operation in block transfer mode when MARA is designated as a block area. Address T Address T Block area 1st block Transfer Consecutive transfer Address B of M bytes or words is performed in response to one request 2nd block Nth block...
Page 182 ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.
Page 183 Start (DTE = DTME = 1) Transfer request? Acquire bus Read address specified by MARA SAID DTSZ MARA=MARA+SAIDE·(–1) ·2 Write to address specified by MARB DAID DTSZ MARB=MARB+DAIDE·(–1) ·2 ETCRAL=ETCRAL–1 ETCRAL=H'00 Release bus ETCRAL=ETCRAH BLKDIR=0 DAID DTSZ MARB=MARB–DAIDE·(–1) ·2 ·ETCRAH SAID DTSZ MARA=MARA–SAIDE·(–1)
Page 184: Block Transfer Mode
For details, see section 5.3.4, DMA Control Register (DMACR). Figure 5-16 shows an example of the setting procedure for block transfer mode. [1] Set each bit in DMABCRH. Block transfer • Set the FAE bit to 1 to select full address mode setting mode.
Page 185: Dmac Activation Sources
5.5.8 DMAC Activation Sources DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The activation sources that can be specified depend on the transfer mode and the channel, as shown in table 5-12. Table 5-12 DMAC Activation Sources Short Address Mode Full Address Mode Block...
Page 186 activation source for more than one channel, the interrupt request flag is cleared when the highest- priority channel is activated first. Transfer requests for other channels are held pending in the DMAC, and activation is carried out in order of priority. When DTE = 0, such as after completion of a transfer, a request from the selected activation source is not sent to the DMAC, regardless of the DTA bit.
Page 187 DACK strobe, without regard to the address. Figure 5-16 shows the data bus in single address mode. HWR, LWR External Address bus to A memory (Read) H8S/2338 Series, H8S/2328 Series, or (Write) H8S/2318 Series to D (high impedance) External device...
Page 188: Basic Dmac Bus Cycles
5.5.9 Basic DMAC Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 5-18. In this example, word- size transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed.
Page 189: Dmac Bus Cycles (Dual Address Mode)
5.5.10 DMAC Bus Cycles (Dual Address Mode) Short Address Mode: Figure 5-19 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space. read read read...
Page 190 Full Address Mode (Cycle Steal Mode): Figure 5-20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. read write read...
Page 191 Full Address Mode (Burst Mode): Figure 5-21 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (burst mode) is performed from external 16- bit, 2-state access space to external 16-bit, 2-state access space. read write read...
Page 192 Full Address Mode (Block Transfer Mode): Figure 5-22 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space. read write read...
Page 193 DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 5-23 shows an example of DREQ pin falling edge activated normal mode transfer. Bus release read write release read write...
Page 194 Figure 5-24 shows an example of DREQ pin falling edge activated block transfer mode transfer. 1 block transfer 1 block transfer Bus release read write dead release read write dead release ø DREQ Address Transfer source Transfer destination Transfer source Transfer destination Idle Read...
Page 195 DREQ Level Activation Timing (Normal Mode): Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 5-25 shows an example of DREQ level activated normal mode transfer. read write read write release release release ø...
Page 196 Figure 5-26 shows an example of DREQ level activated block transfer mode transfer. 1 block transfer 1 block transfer Bus release read write dead release read write dead release ø DREQ Address Transfer source Transfer source Transfer destination Transfer destination Idle Read Write...
Page 197: Dmac Bus Cycles (Single Address Mode)
5.5.11 DMAC Bus Cycles (Single Address Mode) Single Address Mode (Read): Figure 5-27 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read DMA read DMA read...
Page 198 Figure 5-28 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read DMA read DMA read dead ø Address bus DACK TEND Last transfer...
Page 199 Single Address Mode (Write): Figure 5-29 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write DMA write dead ø...
Page 200 Figure 5-30 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write dead ø Address bus DACK TEND Last transfer...
Page 201 DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 5-31 shows an example of DREQ pin falling edge activated single address mode transfer. Bus release DMA single Bus release DMA single Bus release...
Page 202 DREQ Pin Low Level Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 5-32 shows an example of DREQ pin low level activated single address mode transfer. Bus release DMA single Bus release DMA single release...
Page 203: Write Data Buffer Function
5.5.12 Write Data Buffer Function DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel.
Page 204: Dmac Multi-Channel Operation
read single read single read ø Internal address Internal read signal External address DACK Figure 5-34 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation.
Page 205: Relation Between The Dmac And External Bus Requests, Refresh Cycles, And The Dtc
If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 5-13.
Page 206: Nmi Interrupts And Dmac
When DMA cycle reads or writes are accesses to on-chip memory or internal I/O registers, these DMA cycles can be executed at the same time as refresh cycles or external bus release. However, simultaneous operation may not be possible when a write buffer is used. 5.5.15 NMI Interrupts and DMAC When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted.
Page 207: Forced Termination Of Dmac Operation
5.5.16 Forced Termination of DMAC Operation If the DTE bit for the channel currently operating is cleared to 0, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again.
Page 208: Clearing Full Address Mode
5.5.17 Clearing Full Address Mode Figure 5-38 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. [1] Clear both the DTE bit and the DTME bit in Clearing full DMABCRL to 0;...
Page 209: Interrupts
Interrupts The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 5-13 shows the interrupt sources and their priority order. Table 5-13 Interrupt Source Priority Order Interrupt Source Interrupt Interrupt Name Short Address Mode Full Address Mode Priority Order DEND0A Interrupt due to end of...
Page 210: Usage Notes
Usage Notes DMAC Register Access during Operation: Except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, MAC registers should not be written to in a DMA transfer. Module Stop: When the MSTP15 bit in MSTPCR is set to 1, the DMAC clock stops, and the module stop state is entered.
Page 211 • Write Data Buffer Function and DMAC Operation Timing The DMAC can start its next operation during external access using the write data buffer function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are different from the case in which the write data buffer function is disabled. Also, internal bus cycles maybe hidden, and not visible.
Page 212 Activation by Falling Edge on DREQ Pin: DREQ pin falling edge detection is performed in synchronization with DMAC internal operations. The operation is as follows: [1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and switches to [2].
Page 213: Data Transfer Controller
Section 6 Data Transfer Controller Overview The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series include a data transfer controller (DTC). The DTC can be activated for data transfer by an interrupt or software. 6.1.1 Features The features of the DTC are: •...
Page 214: Block Diagram
6.1.2 Block Diagram Figure 6-1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit, 1-state reading and writing of DTC register information.
Page 215: Register Configuration
6.1.3 Register Configuration Table 6-1 summarizes the DTC registers. Table 6-1 DTC Registers Name Abbreviation Initial Value Address* DTC mode register A —* Undefined —* DTC mode register B —* Undefined —* DTC source address register —* Undefined —* DTC destination address register —* Undefined —*...
Page 216: Register Descriptions
Register Descriptions 6.2.1 DTC Mode Register A (MRA) Initial value : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- fined fined fined fined fined fined fined fined — — — — — — — — MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer.
Page 217 Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 Bit 2 Description Normal mode Repeat mode Block transfer mode — Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode.
Page 218: Dtc Mode Register B (Mrb)
6.2.2 DTC Mode Register B (MRB) CHNE DISEL CHNS — — — — — Initial value : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- fined fined fined fined fined fined fined fined — — — — — — — —...
Page 219: Dtc Source Address Register (Sar)
DTC chain transfer Chain transfer only when transfer counter = 0 Bits 4 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series, and should always be written with 0. 6.2.3 DTC Source Address Register (SAR) –...
Page 220: Dtc Transfer Count Register B (Crb)
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA register functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA register is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL).
Page 221: Dtc Vector Register (Dtvecr)
Bit n—DTC Activation Enable (DTCEn) Bit n DTCEn Description DTC activation by this interrupt is disabled (Initial value) [Clearing conditions] • When the DISEL bit is 1 and the data transfer has ended • When the specified number of transfers have ended DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended...
Page 222: Module Stop Control Register (Mstpcr)
Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. Bit 7 SWDTE Description DTC software activation is disabled (Initial value) [Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended DTC software activation is enabled [Holding conditions] •...
Page 223: Operation
Bit 14—Module Stop (MSTP14): Specifies the DTC module stop mode. Bit 14 MSTP14 Description DTC module stop mode cleared (Initial value) DTC module stop mode set Operation 6.3.1 Overview When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information.
Page 224 Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1? CHNS = 0? Transfer counter = 0 or DISEL = 1? Transfer counter = 0? DISEL = 1? Clear activation flag Clear DTCER Interrupt exception handling Figure 6-2 Flowchart of DTC Operation...
Page 225 Table 6-2 Chain Transfer Conditions 1st Transfer 2nd Transfer CHNE CHNS DISEL CHNE CHNS DISEL DTC Transfer — Not 0 — — — — Ends at 1st transfer — — — — — Ends at 1st transfer — — — —...
Page 226 Table 6-3 DTC Functions Address Registers Transfer Transfer Transfer Mode Activation Source* Source Destination • • 24 bits 24 bits Normal mode  One transfer request transfers one byte • TPU TGI • or one word 8-bit timer CMI  Memory addresses are incremented •...
Page 227: Activation Sources
6.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0.
Page 228: Dtc Vector Table
The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip RAM. Note: * Normal mode is not supported in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series.
Page 229 Table 6-5 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Interrupt Vector Vector Interrupt Source Source Number Address DTCE* Priority Write to DTVECR Software DTVECR H'0400+ — High (DTVECR [6:0]<<1) IRQ0 External pin H'0420 DTCEA7 IRQ1 H'0422 DTCEA6 IRQ2 H'0424 DTCEA5...
Page 230 Table 6-5 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs (cont) Origin of Interrupt Vector Vector Interrupt Source Source Number Address DTCE* Priority TGI3A (GR3A compare match/ H'0460 DTCEC5 High input capture) channel 3 TGI3B (GR3B compare match/ H'0462 DTCEC4 input capture) TGI3C (GR3C compare match/ H'0464...
Page 231: Location Of Register Information In Address Space
DTC vector Register information Register information address start address Next transfer Figure 6-4 Correspondence between DTC Vector Address and Register Information 6.3.4 Location of Register Information in Address Space Figure 6-5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address).
Page 232: Normal Mode
6.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 6-6 lists the register information in normal mode and figure 6-6 shows the memory map in normal mode.
Page 233: Repeat Mode
6.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated.
Page 234: Block Transfer Mode
6.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed.
Page 235 First block · SAR or DAR or · Block area · Transfer Nth block Figure 6-8 Memory Map in Block Transfer Mode...
Page 236: Chain Transfer
6.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. It is also possible, by setting both the CHNE bit and CHNS bit to 1, to specify execution of chain transfer only when the transfer counter value is 0. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently.
Page 237: Operation Timing
6.3.9 Operation Timing Figures 6-10 to 6-12 show examples of DTC operation timing. ø DTC activation request request Data transfer Vector read Address Read Write Transfer Transfer information read information write Figure 6-10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ø...
Page 238: Number Of Dtc Execution States
ø DTC activation request request Data transfer Data transfer Vector read Address Read Write Read Write Transfer Transfer Transfer Transfer information information information information read write read write Figure 6-12 DTC Operation Timing (Example of Chain Transfer) 6.3.10 Number of DTC Execution States Table 6-9 lists execution phases for a single DTC data transfer, and table 6-10 shows the number of states required for each execution phase.
Page 239 Table 6-10 Number of States Required for Each Execution Phase Chip Chip On-Chip I/O Access To: Registers External Devices Bus width Access states Execution Vector read — — — 6+2m 2 phase Register — — — — — — — information read/write Byte data read...
Page 240: Procedures For Using Dtc
6.3.11 Procedures for Using DTC Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Set the corresponding bit in DTCER to 1.
Page 241: Examples Of Use Of The Dtc
6.3.12 Examples of Use of the DTC Normal Mode: An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. [1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0).
Page 242 Chain Transfer: An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU’s TGR in the second half.
Page 243 Chain Transfer when Counter = 0: By executing a second data transfer, and performing re- setting of the first data transfer, only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000.
Page 244 Input circuit Input buffer First data transfer register information Chain transfer (counter = 0) Second data Upper 8 bits transfer register of DAR information Figure 6-13 Chain Transfer when Counter = 0...
Page 245 Software Activation: An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. [1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0).
Page 246: Interrupts
Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control.
Page 247: 16-Bit Timer Pulse Unit (Tpu)
Section 7 16-Bit Timer Pulse Unit (TPU) Overview The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series have an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. 7.1.1 Features • Maximum 16-pulse input/output  A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3,...
Page 248 • 26 interrupt sources  For channels 0 and 3, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently  For channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently •...
Page 249 Table 7-1 TPU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 ø/1 ø/1 ø/1 ø/1 ø/1 Count clock ø/1 ø/4 ø/4 ø/4 ø/4 ø/4 ø/4 ø/16 ø/16 ø/16 ø/16 ø/16 ø/16 ø/64 ø/64 ø/64 ø/64 ø/64 ø/64...
Page 250 Table 7-1 TPU Functions (cont) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 TGR2A TGR3A TGR4A TGR5A DMAC TGR0A TGR1A activation compare compare compare compare compare compare match or match or match or match or match or match or input capture...
Page 251: Block Diagram
7.1.2 Block Diagram Figure 7-1 shows a block diagram of the TPU. Interrupt request signals Channel 3: TGI3A Input/output pins TGI3B Channel 3: TIOCA3 TGI3C TIOCB3 TGI3D TIOCC3 TCI3V TIOCD3 Channel 4: TGI4A Channel 4: TIOCA4 TGI4B TIOCB4 TCI4V Channel 5: TIOCA5 TCI4U TIOCB5...
Page 252: Pin Configuration
7.1.3 Pin Configuration Table 7-2 summarizes the TPU pins. Table 7-2 TPU Pins Channel Name Symbol Function Clock input A TCLKA Input External clock A input pin (Channel 1 and 5 phase counting mode A phase input) Clock input B TCLKB Input External clock B input pin...
Page 253 Table 7-2 TPU Pins (cont) Channel Name Symbol Function Input capture/out TIOCA3 TGR3A input capture input/output compare compare match A3 output/PWM output pin Input capture/out TIOCB3 TGR3B input capture input/output compare compare match B3 output/PWM output pin Input capture/out TIOCC3 TGR3C input capture input/output compare compare match C3 output/PWM output pin...
Page 254: Register Configuration
7.1.4 Register Configuration Table 7-3 summarizes the TPU registers. Table 7-3 TPU Registers Channel Name Abbreviation Initial Value Address * Timer control register 0 TCR0 H'00 H'FFD0 Timer mode register 0 TMDR0 H'C0 H'FFD1 Timer I/O control register 0H TIOR0H H'00 H'FFD2 Timer I/O control register 0L...
Page 255 Table 7-3 TPU Registers (cont) Channel Name Abbreviation Initial Value Address* Timer control register 3 TCR3 H'00 H'FE80 Timer mode register 3 TMDR3 H'C0 H'FE81 Timer I/O control register 3H TIOR3H H'00 H'FE82 Timer I/O control register 3L TIOR3L H'00 H'FE83 Timer interrupt enable register 3 TIER3 H'40...
Page 256: Register Descriptions
Register Descriptions 7.2.1 Timer Control Registers (TCR) Channel 0: TCR0 Channel 3: TCR3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value : Channel 1: TCR1 Channel 2: TCR2 Channel 4: TCR4 Channel 5: TCR5 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1...
Page 257 Bits 7, 6, and 5—Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the TCNT counter clearing source. Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description 0, 3 TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture...
Page 258 Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. ø/4 both edges = ø/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority.
Page 259 Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on ø/1 (Initial value) Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input...
Page 260 Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on ø/1 (Initial value) Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input Internal clock: counts on ø/1024 Internal clock: counts on ø/256 Internal clock: counts on ø/4096...
Page 261: Timer Mode Registers (Tmdr)
7.2.2 Timer Mode Registers (TMDR) Channel 0: TMDR0 Channel 3: TMDR3 — — Initial value : — — Channel 1: TMDR1 Channel 2: TMDR2 Channel 4: TMDR4 Channel 5: TMDR5 — — — — Initial value : — — — —...
Page 262 Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved.
Page 263: Timer I/O Control Registers (Tior)
7.2.3 Timer I/O Control Registers (TIOR) Channel 0: TIOR0H Channel 1: TIOR1 Channel 2: TIOR2 Channel 3: TIOR3H Channel 4: TIOR4 Channel 5: TIOR5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : Channel 0: TIOR0L Channel 3: TIOR3L IOD3 IOD2 IOD1...
Page 264 Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD. Bit 7 Bit 6 Bit 5 Bit 4...
Page 265 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOD3 IOD2 IOD1 IOD0 Description TGR0D is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register* Toggle output at compare match Output disabled Initial output is 1...
Page 266 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description TGR1B is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 267 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description TGR3B is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 268 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOD3 IOD2 IOD1 IOD0 Description TGR3D is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register* Toggle output at compare match Output disabled Initial output is 1...
Page 269 Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description TGR4B is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 270 Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC. Bit 3 Bit 2 Bit 1 Bit 0 Channel...
Page 271 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOC3 IOC2 IOC1 IOC0 Description TGR0C is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register* Toggle output at compare match Output disabled Initial output is 1...
Page 272 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR1A is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 273 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR3A is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 274 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOC3 IOC2 IOC1 IOC0 Description TGR3C is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register* Toggle output at compare match Output disabled Initial output is 1...
Page 275 Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR4A is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...
Page 276: Timer Interrupt Enable Registers (Tier)
7.2.4 Timer Interrupt Enable Registers (TIER) Channel 0: TIER0 Channel 3: TIER3 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value : — — Channel 1: TIER1 Channel 2: TIER2 Channel 4: TIER4 Channel 5: TIER5 TTGE — TCIEU TCIEV —...
Page 277 Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the TCFU bit when the TCFU bit in TSR is set to 1 in channels 1 and 2. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 TCIEU Description...
Page 278: Timer Status Registers (Tsr)
Bit 1—TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. Bit 1 TGIEB Description Interrupt requests (TGIB) by TGFB disabled (Initial value) Interrupt requests (TGIB) by TGFB enabled Bit 0—TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1.
Page 279 The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has six TSR registers, one for each channel. The TSR registers are initialized to H'C0 by a reset and in hardware standby mode. Bit 7—Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5.
Page 280 Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGFD Description...
Page 281 Bit 1—Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture or compare match. Bit 1 TGFB Description [Clearing conditions] (Initial value) • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 •...
Page 282: Timer Counters (Tcnt)
7.2.6 Timer Counters (TCNT) Channel 0: TCNT0 (up-counter) Channel 1: TCNT1 (up/down-counter*) Channel 2: TCNT2 (up/down-counter*) Channel 3: TCNT3 (up-counter) Channel 4: TCNT4 (up/down-counter*) Channel 5: TCNT5 (up/down-counter*) Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel.
Page 283: Timer Start Register (Tstr)
7.2.8 Timer Start Register (TSTR) — — CST5 CST4 CST3 CST2 CST1 CST0 Initial value : — — TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. TSTR is initialized to H'00 by a reset, and in hardware standby mode. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.
Page 284: Module Stop Control Register (Mstpcr)
Bits 5 to 0—Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels* , and synchronous clearing through counter clearing on another channel* are possible.
Page 285: Interface To Bus Master
Interface to Bus Master 7.3.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 7-2.
Page 286 Examples of 8-bit register access operation are shown in figures 7-3, 7-4, and 7-5. Internal data bus Module Bus interface master data bus Figure 7-3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)] Internal data bus Module master Bus interface data bus...
Page 287: Operation
Operation 7.4.1 Overview Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Synchronous Operation: When synchronous operation is designated for a channel, TCNT for that channel performs synchronous presetting.
Page 288: Basic Functions
7.4.2 Basic Functions Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. • Example of count operation setting procedure Figure 7-6 shows an example of the count operation setting procedure.
Page 289 • Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up- count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1.
Page 290 Figure 7-8 illustrates periodic counter operation. Counter cleared by TGR TCNT value compare match H'0000 Time CST bit Flag cleared by software or DTC/DMAC activation Figure 7-8 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match.
Page 291 • Examples of waveform output operation Figure 7-10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
Page 292 Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel’s counter input clock or compare match signal as the input capture source.
Page 293 • Example of input capture operation Figure 7-13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Page 294: Synchronous Operation
7.4.3 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation.
Page 295 Example of Synchronous Operation: Figure 7-15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Page 296: Buffer Operation
7.4.4 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 7-5 shows the register combinations used in buffer operation.
Page 297 • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 7-17. Input capture signal Timer general...
Page 298 Examples of Buffer Operation • When TGR is an output compare register Figure 7-19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
Page 299 • When TGR is an input capture register Figure 7-20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
Page 300: Cascaded Operation
7.4.5 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Page 301 Examples of Cascaded Operation: Figure 7-22 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated as input capture registers, and TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.
Page 302: Pwm Modes
7.4.6 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register.
Page 303 Table 7-7 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 TGR0A TIOCA0 TIOCA0 TGR0B TIOCB0 TGR0C TIOCC0 TIOCC0 TGR0D TIOCD0 TGR1A TIOCA1 TIOCA1 TGR1B TIOCB1 TGR2A TIOCA2 TIOCA2 TGR2B TIOCB2 TGR3A TIOCA3 TIOCA3 TGR3B TIOCB3...
Page 304 Example of PWM Mode Setting Procedure: Figure 7-24 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to PWM mode TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
Page 305 TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 7-25 Example of PWM Mode Operation (1) Figure 7-26 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM waveform.
Page 306 Figure 7-27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when period register and duty register compare matches occur simultaneously TCNT value TGRB rewritten...
Page 307: Phase Counting Mode
7.4.7 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Page 308 Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. • Phase counting mode 1 Figure 7-29 shows an example of phase counting mode 1 operation, and table 7-9 summarizes the TCNT up/down-count conditions.
Page 309 • Phase counting mode 2 Figure 7-30 shows an example of phase counting mode 2 operation, and table 7-10 summarizes the TCNT up/down-count conditions. TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) TCNT value Up-count Down-count...
Page 310 • Phase counting mode 3 Figure 7-31 shows an example of phase counting mode 3 operation, and table 7-11 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count...
Page 311 • Phase counting mode 4 Figure 7-32 shows an example of phase counting mode 4 operation, and table 7-12 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count...
Page 312 Phase Counting Mode Application Example: Figure 7-33 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB.
Page 313 Channel 1 TCLKA Edge TCNT1 detection TCLKB circuit TGR1A (speed period capture) TGR1B (position period capture) TCNT0 TGR0A (speed control period) – TGR0C – (position control period) TGR0B (pulse width capture) TGR0D (buffer operation) Channel 0 Figure 7-33 Phase Counting Mode Application Example...
Page 314: Interrupts
Interrupts 7.5.1 Interrupt Sources and Priorities There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
Page 315 Table 7-13 TPU Interrupts Interrupt DMAC Channel Source Description Activation Activation Priority TGI0A TGR0A input capture/compare match Possible Possible High TGI0B TGR0B input capture/compare match Not possible Possible TGI0C TGR0C input capture/compare match Not possible Possible TGI0D TGR0D input capture/compare match Not possible Possible TCI0V TCNT0 overflow Not possible Not possible...
Page 316: Dtc/Dmac Activation
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
Page 317: Operation Timing
Operation Timing 7.6.1 Input/Output Timing TCNT Count Timing: Figure 7-34 shows TCNT count timing in internal clock operation, and figure 7-35 shows TCNT count timing in external clock operation. ø Falling edge Rising edge Internal clock TCNT input clock TCNT N–1 Figure 7-34 Count Timing in Internal Clock Operation ø...
Page 318 Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin.
Page 319 Timing for Counter Clearing by Compare Match/Input Capture: Figure 7-38 shows the timing when counter clearing by compare match occurrence is specified, and figure 7-39 shows the timing when counter clearing by input capture occurrence is specified. ø Compare match signal Counter clear signal H'0000...
Page 320 Buffer Operation Timing: Figures 7-40 and 7-41 show the timing in buffer operation. ø TCNT Compare match signal TGRA, TGRB TGRC, TGRD Figure 7-40 Buffer Operation Timing (Compare Match) ø Input capture signal TCNT TGRA, TGRB TGRC, TGRD Figure 7-41 Buffer Operation Timing (Input Capture)
Page 321: Interrupt Signal Timing
7.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 7-42 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. ø TCNT input clock TCNT Compare match signal...
Page 322 TGF Flag Setting Timing in Case of Input Capture: Figure 7-43 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. ø Input capture signal TCNT TGF flag TGI interrupt Figure 7-43 TGI Interrupt Timing (Input Capture)
Page 323 TCFV Flag/TCFU Flag Setting Timing: Figure 7-44 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 7-45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing.
Page 324 Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 7-46 shows the timing for status flag clearing by the CPU, and figure 7-47 shows the timing for status flag clearing by the DTC or DMAC.
Page 325: Usage Notes
Usage Notes Note that the kinds of operation and contention described below can occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width.
Page 326 Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 7-49 shows the timing in this case. TCNT write cycle ø...
Page 327 Contention between TCNT Write and Increment Operations: If incrementing occurs in the T state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 7-50 shows the timing in this case. TCNT write cycle ø...
Page 328 Contention between TGR Write and Compare Match: If a compare match occurs in the T state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 7-51 shows the timing in this case.
Page 329 Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 7-52 shows the timing in this case. TGR write cycle ø...
Page 330 Contention between TGR Read and Input Capture: If the input capture signal is generated in the T state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 7-53 shows the timing in this case. TGR read cycle ø...
Page 331 Contention between TGR Write and Input Capture: If the input capture signal is generated in the T state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 7-54 shows the timing in this case. TGR write cycle ø...
Page 332 Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 7-55 shows the timing in this case. Buffer register write cycle ø...
Page 333 Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 7-56 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.
Page 334 TCFV flag Figure 7-57 Contention between TCNT Write and Overflow Multiplexing of I/O Pins: In the H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin.
Page 335: Programmable Pulse Generator (Ppg)
Section 8 Programmable Pulse Generator (PPG) Overview The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series have a built-in programmable pulse generator (PPG) that provides pulse outputs by using the 16-bit timer-pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate both simultaneously and independently.
Page 336: Block Diagram
8.1.2 Block Diagram Figure 8-1 shows a block diagram of the PPG. Compare match signals NDERH NDERL Control logic PO15 Pulse output PO14 PO13 pins, group 3 Internal PO12 PODRH NDRH PO11 data bus Pulse output PO10 pins, group 2 Pulse output pins, group 1 PODRL...
Page 337: Pin Configuration
8.1.3 Pin Configuration Table 8-1 summarizes the PPG pins. Table 8-1 PPG Pins Name Symbol Function Pulse output 0 Output Group 0 pulse output Pulse output 1 Output Pulse output 2 Output Pulse output 3 Output Pulse output 4 Output Group 1 pulse output Pulse output 5 Output...
Page 338: Registers
8.1.4 Registers Table 8-2 summarizes the PPG registers. Table 8-2 PPG Registers Name Abbreviation Initial Value Address* PPG output control register H'FF H'FF46 PPG output mode register H'F0 H'FF47 Next data enable register H NDERH H'00 H'FF48 Next data enable register L NDERL H'00 H'FF49...
Page 339: Register Descriptions
Register Descriptions 8.2.1 Next Data Enable Registers H and L (NDERH, NDERL) NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value : NDERL NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial value : NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a bit-by-bit basis.
Page 340: Output Data Registers H And L (Podrh, Podrl)
NDERL Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable pulse output on a bit-by-bit basis. Bits 7 to 0 NDER7 to NDER0 Description Pulse outputs PO7 to PO0 are disabled (NDR7 to NDR0 are not transferred to POD7 to POD0) (Initial value) Pulse outputs PO7 to PO0 are enabled (NDR7 to NDR0 are transferred to...
Page 341: Next Data Registers H And L (Ndrh, Ndrl)
8.2.3 Next Data Registers H and L (NDRH, NDRL) NDRH and NDRL are 8-bit readable/writable registers that store the next data for pulse output. During pulse output, the contents of NDRH and NDRL are transferred to the corresponding bits in PODRH and PODRL when the TPU compare match event specified by PCR occurs.
Page 342 Address H'FF4D NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value : Address H'FF4F — — — — — — — — Initial value : — — — — — — — — Different Triggers for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits in NDRH (group 3) is H'FF4C and the address of the lower 4 bits (group 2) is H'FF4E.
Page 343: Ppg Output Control Register (Pcr)
Address H'FF4D NDR7 NDR6 NDR5 NDR4 — — — — Initial value : — — — — Address H'FF4F — — — — NDR3 NDR2 NDR1 NDR0 Initial value : — — — — 8.2.5 PPG Output Control Register (PCR) G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : PCR is an 8-bit readable/writable register that selects output trigger signals for PPG outputs on a...
Page 344 Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare match that triggers pulse output group 2 (pins PO11 to PO8). Description Bit 5 Bit 4 G2CMS1 G2CMS0 Output Trigger for Pulse Output Group 2 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2...
Page 345: Ppg Output Mode Register (Pmr)
8.2.6 PPG Output Mode Register (PMR) G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV Initial value : PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping operation for each group. The output trigger period of a non-overlapping operation PPG output waveform is set in TGRB and the non-overlap margin is set in TGRA.
Page 346 Bit 5—Group 1 Inversion (G1INV): Selects direct output or inverted output for pulse output group 1 (pins PO7 to PO4). Bit 5 G1INV Description Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL) Direct output for pulse output group 1 (high-level output at pin for a 1 in PODRL) (Initial value) Bit 4—Group 0 Inversion (G0INV): Selects direct output or inverted output for pulse output...
Page 347: Port 1 Data Direction Register (P1Ddr)
Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse output group 1 (pins PO7 to PO4). Bit 1 G1NOV Description Normal operation in pulse output group 1 (output values updated at compare match A in the selected TPU channel) (Initial value) Non-overlapping operation in pulse output group 1 (independent 1 and 0 output at compare match A or B in the selected TPU channel)
Page 348: Port 2 Data Direction Register (P2Ddr)
8.2.8 Port 2 Data Direction Register (P2DDR) P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. Port 2 is multiplexed with pins PO7 to PO0. Bits corresponding to pins used for PPG output must be set to 1.
Page 349: Operation
Operation 8.3.1 Overview PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. In this state the corresponding PODR contents are output. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values.
Page 350: Output Timing
8.3.2 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 8-3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. ø...
Page 351: Normal Pulse Output
8.3.3 Normal Pulse Output Sample Setup Procedure for Normal Pulse Output: Figure 8-4 shows a sample procedure for setting up normal pulse output. [1] Set TIOR to make TGRA an output Normal PPG output compare register (with output disabled). Select TGR functions [2] Set the PPG output trigger period.
Page 352 Example of Normal Pulse Output (Example of Five-Phase Pulse Output): Figure 8-5 shows an example in which pulse output is used for cyclic five-phase pulse output. Compare match TCNT value TCNT TGRA H'0000 Time NDRH PODRH PO15 PO14 PO13 PO12 PO11 Figure 8-5 Normal Pulse Output Example (Five-Phase Pulse Output) [1] Set up the TPU channel to be used as the output trigger channel so that TGRA is an output...
Page 353: Non-Overlapping Pulse Output
8.3.4 Non-Overlapping Pulse Output Sample Setup Procedure for Non-Overlapping Pulse Output: Figure 8-6 shows a sample procedure for setting up non-overlapping pulse output. [1] Set TIOR to make TGRA and Non-overlapping PPG output TGRB an output compare registers (with output disabled). Select TGR functions [2] Set the pulse output trigger period in TGRB and the non-overlap...
Page 354 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non- Overlapping Output): Figure 8-7 shows an example in which pulse output is used for four-phase complementary non-overlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 Time NDRH PODRH Non-overlap margin PO15 PO14 PO13...
Page 355 [1] Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt.
Page 356: Inverted Pulse Output
8.3.5 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 8-8 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 8-7.
Page 357: Pulse Output Triggered By Input Capture
8.3.6 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal.
Page 358: Usage Notes
Usage Notes 8.4.1 Operation of Pulse Output Pins Pins PO0 to PO15 are also used for other supporting functions such as the TPU. When output by another supporting function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins.
Page 359 Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC or DMAC.
Page 360: Overview
Section 9 8-Bit Timers Overview The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series include an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare match events.
Page 361: Block Diagram
9.1.2 Block Diagram Figure 9-1 shows a block diagram of the 8-bit timer module. External clock source Internal clock sources TMCI0 ø/8 TMCI1 ø/64 ø/8192 Clock 1 Clock select Clock 0 TCORA0 TCORA1 Compare match A1 Comparator A0 Comparator A1 Compare match A0 Overflow 1 TMO0...
Page 362: Pin Configuration
9.1.3 Pin Configuration Table 9-1 summarizes the input and output pins of the 8-bit timer module. Table 9-1 Input and Output Pins of 8-Bit Timer Channel Name Symbol Function Timer output pin 0 TMO0 Output Outputs at compare match Timer clock input pin 0 TMCI0 Input Inputs external clock for counter...
Page 363: Timer Counters 0 And 1 (Tcnt0, Tcnt1)
Register Descriptions 9.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) TCNT0 TCNT1 Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT0 and TCNT1 are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source.
Page 364: Time Constant Registers B0 And B1 (Tcorb0, Tcorb1)
TCORA0 and TCORA1 are each initialized to H'FF by a reset and in hardware standby mode. 9.2.3 Time Constant Registers B0 and B1 (TCORB0, TCORB1) TCORB0 TCORB1 Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0 and TCORB1 are 8-bit readable/writable registers.
Page 365 Bit 7 CMIEB Description CMFB interrupt requests (CMIB) are disabled (Initial value) CMFB interrupt requests (CMIB) are enabled Bit 6—Compare Match Interrupt Enable A (CMIEA): Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag in TCSR is set to 1. Bit 6 CMIEA Description...
Page 366: Timer Control/Status Registers 0 And 1 (Tcsr0, Tcsr1)
Some functions differ between channel 0 and channel 1. Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 Description Clock input disabled (Initial value) Internal clock, counted at falling edge of ø/8 Internal clock, counted at falling edge of ø/64 Internal clock, counted at falling edge of ø/8192 For channel 0: count at TCNT1 overflow signal* For channel 1: count at TCNT0 compare match A*...
Page 367 Bit 7—Compare Match Flag B (CMFB): Status flag indicating whether the values of TCNT and TCORB match. Bit 7 CMFB Description [Clearing conditions] (Initial value) • Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB • When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 [Setting condition] Set when TCNT matches TCORB...
Page 368 Bit 4—A/D Trigger Enable (ADTE) (TCSR0 Only): Selects enabling or disabling of A/D converter start requests by compare match A. In TCSR1, this bit is reserved: it is always read as 1 and cannot be modified. Bit 4 ADTE Description A/D converter start requests by compare match A are disabled (Initial value) A/D converter start requests by compare match A are enabled...
Page 369: Module Stop Control Register (Mstpcr)
9.2.6 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP12 bit in MSTPCR is set to 1, the 8-bit timer operation stops at the end of the bus cycle and a transition is made to module stop mode.
Page 370: Operation
Operation 9.3.1 TCNT Incrementation Timing TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (ø/8, ø/64, or ø/8192) divided from the system clock (ø) can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 9-2 shows the count timing.
Page 371: Compare Match Timing
ø External clock input pin Clock input to TCNT TCNT N–1 Figure 9-3 Count Timing for External Clock Input 9.3.2 Compare Match Timing Setting of Compare Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated.
Page 372 Timer Output Timing: When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. Figure 9-5 shows the timing when the output is set to toggle at compare match A.
Page 373: Timing Of Tcnt External Reset
9.3.3 Timing of TCNT External Reset TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 9-7 shows the timing of this operation.
Page 374: Operation With Cascaded Connection
9.3.5 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B’100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit timer mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match counter mode).
Page 375: Interrupts
Interrupts 9.4.1 Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 9-3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR, and independent interrupt requests are sent for each to the interrupt controller.
Page 376: Usage Notes
TCNT H'FF Counter clear TCORA TCORB H'00 Figure 9-9 Example of Pulse Output Usage Notes Note that the following kinds of contention can occur in the 8-bit timer module. 9.6.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed.
Page 377: Contention Between Tcnt Write And Increment
9.6.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 9-11 shows this operation. TCNT write cycle by CPU ø...
Page 378: Contention Between Tcor Write And Compare Match
9.6.3 Contention between TCOR Write and Compare Match During the T state of a TCOR write cycle, the TCOR write has priority and the compare match signal is inhibited even if a compare match event occurs. Figure 9-12 shows this operation. TCOR write cycle by CPU ø...
Page 379: Contention Between Compare Matches A And B
9.6.4 Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 9-4.
Page 380 Table 9-5 Switching of Internal Clock and TCNT Operation Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from Clock before low to low* switchover Clock after switchover TCNT clock TCNT CKS bit write Switching from Clock before low to high* switchover...
Page 381: Interrupts And Module Stop Mode
Table 9-5 Switching of Internal Clock and TCNT Operation (cont) Timing of Switchover by Means of CKS1 and CKS0 Bits TCNT Clock Operation Switching from high Clock before to high switchover Clock after switchover TCNT clock TCNT CKS bit write Notes: 1.
Page 382: Section 10 Watchdog Timer
If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or not the entire H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip is reset at the same time • Interrupt generation when in interval timer mode If the counter overflows, the WDT generates an interval timer interrupt •...
Page 383: Block Diagram
10.1.2 Block Diagram Figure 10-1 shows a block diagram of the WDT. Overflow ø/2 Interrupt ø/64 WOVI control ø/128 (interrupt request signal) ø/512 Clock Clock select ø/2048 ø/8192 ø/32768 WDTOVF Reset ø/131072 control Internal reset signal Internal clock sources RSTCSR TCNT TSCR interface...
Page 384: Pin Configuration
10.1.3 Pin Configuration Table 10-1 describes the WDT output pin. Table 10-1 WDT Pin Name Symbol Function WDTOVF* Output Watchdog timer overflow Outputs counter overflow signal in watchdog timer mode Note: * The WDTOVF output function is not available in all models; please check the reference manual for the relevant model for confirmation.
Page 385 10.2 Register Descriptions 10.2.1 Timer Counter (TCNT) Initial value : TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), either the watchdog timer overflow signal (WDTOVF)* or an interval timer interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR.
Page 386 Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00, when in interval timer mode. This flag cannot be set during watchdog timer operation. Bit 7 Description [Clearing condition] (Initial value) Cleared by reading TCSR when OVF = 1, then writing 0 to OVF [Setting condition] Set when TCNT overflows (changes from H'FF to H'00) in interval timer mode Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or...
Page 387: Reset Control/Status Register (Rstcsr)
Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources, obtained by dividing the system clock (ø), for input to TCNT. Description Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 Clock...
Page 388: Notes On Register Access
(Initial value) Reset signal is generated if TCNT overflows Note: * The modules within the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip are not reset, but TCNT and TCSR within the WDT are reset. Bit 5— Reserved: Read-only bit.
Page 389 TCNT write H'5A Write data Address: H'FFBC TCSR write H'A5 Write data Address: H'FFBC Figure 10-2 Writing to TCNT and TCSR Writing to RSTCSR: RSTCSR must be written to by a word transfer instruction to address H'FFBE. It cannot be written to with byte instructions. Figure 10-3 shows the format of data written to RSTCSR.
Page 390: Operation
10.3 Operation 10.3.1 Operation in Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflow occurs. This ensures that TCNT does not overflow while the system is operating normally.
Page 391 TCNT count Overflow H'FF Time H'00 WT/IT=1 WOVF=1 H'00 written WT/IT=1 H'00 written TME=1 to TCNT TME=1 to TCNT WDTOVF * internal reset are generated WDTOVF signal * 132 states * Internal reset signal * 518 states Legend : Timer mode select bit WT/IT : Timer enable bit Notes: 1.
Page 392: Operation In Interval Timer Mode
10.3.2 Operation in Interval Timer Mode To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 10-5.
Page 393: Timing Of Watchdog Timer Overflow Flag (Wovf) Setting
WDTOVF signal goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip. Figure 10-7 shows the timing in this case.
Page 394: Changing Value Of Cks2 To Cks0
TCNT write cycle ø Address Internal write signal TCNT input clock TCNT Counter write data Figure 10-8 Contention between TCNT Write and Increment 10.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors may occur in the incrementation.
Page 395: System Reset By Wdtovf Signal
System Reset by WDTOVF Signal* 10.5.4 If the WDTOVF output signal* is input to the RES pin of the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip, the chip will not be initialized correctly. Make sure that the WDTOVF signal* is not input logically to the RES pin. To reset the entire system by means of the WDTOVF signal*, use the circuit shown in figure 10-9.
Page 396: Section 11 Serial Communication Interface (Sci)
Section 11 Serial Communication Interface (SCI) 11.1 Overview The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series are equipped with a serial communication interface (SCI) that can handle both asynchronous and synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function).
Page 397 • Full-duplex communication capability  The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously  Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data •...
Page 398: Block Diagram
11.1.2 Block Diagram Figure 11-1 shows a block diagram of the SCI. Internal Module data bus data bus SCMR ø ø/4 Baud rate generator ø/16 Transmission/ ø/64 reception control Parity generation Clock Parity check External clock Legend SCMR : Smart card mode register : Receive shift register : Receive data register : Transmit shift register...
Page 399: Pin Configuration
11.1.3 Pin Configuration Table 11-1 shows the serial pins for each SCI channel. Table 11-1 SCI Pins Channel* Pin Name Symbol Function Serial clock pin 0 SCK0 SCI0 clock input/output Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output...
Page 400: Register Configuration
11.1.4 Register Configuration The SCI has the internal registers shown in table 11-2. These registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the transmitter/receiver. Table 11-2 SCI Registers Channel* Name Abbreviation...
Page 401: Register Descriptions
11.2 Register Descriptions 11.2.1 Receive Shift Register (RSR) — — — — — — — — RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data.
Page 402: Transmit Shift Register (Tsr)
11.2.3 Transmit Shift Register (TSR) — — — — — — — — TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically.
Page 403: Serial Mode Register (Smr)
11.2.5 Serial Mode Register (SMR) STOP CKS1 CKS0 Initial value : SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset and in hardware standby mode.
Page 404 Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode and with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting.
Page 405 Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bits setting is only valid in asynchronous mode. If synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP Description...
Page 406: Serial Control Register (Scr)
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from ø, ø/4, ø/16, and ø/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 11.2.8, Bit Rate Register.
Page 407 Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 Description Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled*...
Page 408 Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE Description...
Page 409 Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin.
Page 410: Serial Status Register (Ssr)
11.2.7 Serial Status Register (SSR) TDRE RDRF ORER TEND MPBT Initial value : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits.
Page 411 Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER Description [Clearing condition] (Initial value)* When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1* Notes: 1.
Page 412 Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 3 Description [Clearing condition] (Initial value)* When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR* Notes: 1.
Page 413: Bit Rate Register (Brr)
Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting, and in synchronous mode.
Page 414 Table 11-3 BRR Settings for Various Bit Rates (Asynchronous Mode) ø = 2 MHz ø = 2.097152 MHz ø = 2.4576 MHz ø = 3 MHz Bit Rate Error Error Error Error (bits/s) 0.03 –0.04 1 –0.26 1 0.03 0.16 0.21 0.00 0.16...
Page 415 Table 11-3 BRR Settings for Various Bit Rates (Asynchronous Mode) (cont) ø = 6 MHz ø = 6.144 MHz ø = 7.3728 MHz ø = 8 MHz Bit Rate Error Error Error Error (bits/s) –0.44 2 0.08 –0.07 2 0.03 0.16 0.00 0.00...
Page 416 Table 11-3 BRR Settings for Various Bit Rates (Asynchronous Mode) (cont) ø = 14 MHz ø = 14.7456 MHz ø = 16 MHz ø = 17.2032 MHz Bit Rate Error Error Error Error (bits/s) –0.17 3 0.70 0.03 0.48 0.16 0.00 0.16 0.00...
Page 417 Table 11-4 BRR Settings for Various Bit Rates (Synchronous Mode) ø = 2 MHz ø = 4 MHz ø = 8 MHz ø = 10 MHz ø = 16 MHz ø = 20 MHz ø = 25 MHz* Bit Rate (bits/s) n —...
Page 418 The BRR setting is found from the following formulas. Asynchronous mode: ø × 10 – 1 64 × 2 × B 2n–1 Synchronous mode: ø × 10 – 1 8 × 2 × B 2n–1 Where B: Bit rate (bits/s) N: BRR setting for baud rate generator (0 ≤...
Page 419 Table 11-5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 11-6 and 11-7 show the maximum bit rates with external clock input. Table 11-5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ø (MHz) Maximum Bit Rate (bits/s) 62500 2.097152 65536...
Page 420 Table 11-6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 0.7500 46875 3.6864 0.9216 57600 1.0000 62500 4.9152 1.2288 76800 1.2500 78125 1.5000 93750...
Page 421: Smart Card Mode Register (Scmr)
Table 11-7 Maximum Bit Rate with External Clock Input (Synchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 0.3333 333333.3 0.6667 666666.7 1.0000 1000000.0 1.3333 1333333.3 1.6667 1666666.7 2.0000 2000000.0 2.3333 2333333.3 2.6667 2666666.7 3.0000 3000000.0 3.3333 3333333.3 4.1667 4166666.7...
Page 422 Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. This bit is valid when 8-bit data is used as the transmit/receive format. Bit 3 SDIR Description TDR contents are transmitted LSB-first (Initial value) Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level.
Page 423: Module Stop Control Register (Mstpcr)
11.2.10 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the corresponding bit of bits MSTP7 to MSTP5 is set to 1, SCI operation stops at the end of the bus cycle and a transition is made to module stop mode.
Page 424: Operation
11.3 Operation 11.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SMR as shown in table 11-8.
Page 425 Table 11-8 SMR Settings and Serial Transfer Format Selection SMR Settings SCI Transfer Format Multi- Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data processor Parity Stop Bit STOP Mode Length Length Asynchronous 8-bit data 1 bit mode 2 bits 1 bit 2 bits...
Page 426: Operation In Asynchronous Mode
11.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis.
Page 427 Table 11-10 Serial Transfer Formats (Asynchronous Mode) SMR Settings Serial Transfer Format and Frame Length STOP 8-bit data STOP 8-bit data STOP STOP 8-bit data P STOP 8-bit data P STOP STOP 7-bit data STOP 7-bit data STOP STOP 7-bit data STOP 7-bit data STOP...
Page 428 Clock: Either an internal clock generated by the built-in baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 11-9.
Page 429 Figure 11-4 shows a sample SCI initialization flowchart. [1] Set the clock selection in SCR. Start of initialization Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Clear TE and RE bits in SCR to 0 When the clock is selected in asynchronous mode, it is output Set CKE1 and CKE0 bits in SCR...
Page 430 • Serial data transmission (asynchronous mode) Figure 11-5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start of transmission output pin.
Page 431 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Page 432 Figure 11-6 shows an example of the operation for transmission in asynchronous mode. Start Data Parity Stop Start Data Parity Stop Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt TEI interrupt request generated TDRE flag cleared to 0 in request generated request generated...
Page 433 • Serial data reception (asynchronous mode) Figure 11-7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start of reception input pin.
Page 434 Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCR to 0 PER = 1? Parity error handling Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 11-7 Sample Serial Reception Flowchart (cont)
Page 435 In serial reception, the SCI operates as described below. [1] The SCI monitors the communication line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received.
Page 436 Table 11-11 Receive Error Conditions Receive Error Abbreviation Condition Data Transfer Overrun error ORER When the next data reception is Receive data is not completed while the RDRF flag transferred from RSR to in SSR is set to 1 Framing error When the stop bit is 0 Receive data is transferred from RSR to RDR...
Page 437: Multiprocessor Communication Function
11.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing a single serial communication line.
Page 438 Transmitting station Serial communication line Receiving Receiving Receiving Receiving station A station B station C station D (ID= 01) (ID= 02) (ID= 03) (ID= 04) Serial H'01 H'AA data (MPB= 1) (MPB= 0) ID transmission cycle= Data transmission cycle= receiving station Data transmission to specification receiving station specified by ID...
Page 439 SCI initialization: Initialization The TxD pin is automatically designated as the transmit data Start of transmission output pin. After the TE bit is set to 1, a frame of 1s is output, and Read TDRE flag in SSR transmission is enabled. SCI status check and transmit TDRE = 1? data write:...
Page 440 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Page 441 Figure 11-11 shows an example of SCI operation for transmission using the multiprocessor format. Multi- Multi- proces- Start Data Stop Start Data proces- Stop sor bit Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR TXI interrupt TEI interrupt request generated and TDRE flag cleared to...
Page 442 SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start of reception input pin. ID reception cycle: Read MPIE bit in SCR Set the MPIE bit in SCR to 1. Read ORER and FER flags in SSR SCI status check, ID reception and comparison: FER ∨...
Page 443 Error handling ORER = 1? Overrun error handling FER = 1? Break? Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 <End> Figure 11-12 Sample Multiprocessor Serial Reception Flowchart (cont)
Page 444 Figure 11-13 shows an example of SCI operation for multiprocessor format reception. Start Data (ID1) Stop Start Data (Data1) Stop Idle state (mark state) MPIE RDRF value MPIE = 0 RXI interrupt RDR data read If not this station’s ID, RXI interrupt request is request and RDRF flag...
Page 445: Operation In Synchronous Mode
11.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer.
Page 446 Clock: Either an internal clock generated by the built-in baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 11-9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.
Page 447 Data Transfer Operations • SCI initialization (synchronous mode) Before transmitting or receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Page 448 • Serial data transmission (synchronous mode) Figure 11-16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. [1] SCI initialization: Initialization The TxD pin is automatically designated as the transmit data output Start of transmission pin.
Page 449 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Page 450 Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt Data written to TDR TXI interrupt TEI interrupt request generated and TDRE flag request generated request generated cleared to 0 in TXI interrupt handling routine 1 frame...
Page 451 SCI initialization: Initialization The RxD pin is automatically designated as the receive data Start of reception input pin. [2] [3] Receive error handling: Read ORER flag in SSR If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error handling, clear the ORER flag to ORER = 1?
Page 452 In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR.
Page 453 SCI initialization: Initialization The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the Start of transmission/reception receive data input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR SCI status check and transmit data write: Read SSR and check that the...
Page 454: Sci Interrupts
11.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 11-12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of interrupt request is sent to the interrupt controller independently.
Page 455 Table 11-12 SCI Interrupt Sources Interrupt DMAC* Channel* Source Description Activation Activation Priority* Interrupt due to receive error High (ORER, FER, or PER) possible possible Interrupt due to receive data full Possible Possible state (RDRF) Interrupt due to transmit data empty Possible Possible state (TDRE)
Page 456: Usage Notes
11.5 Usage Notes The following points should be noted when using the SCI. Relation between Writes to TDR and the TDRE Flag: The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.
Page 457 Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set.
Page 458 16 clocks 8 clocks 15 0 15 0 Internal base clock Receive data Start bit (RxD) Synchronization sampling timing Data sampling timing Figure 11-21 Receive Data Sampling Timing in Asynchronous Mode Thus the receive margin in asynchronous mode is given by formula (1) below. | D –...
Page 459 Restrictions on Use of DMAC or DTC • When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 ø clock cycles after TDR is updated by the DMAC or DTC. Misoperation may occur if the transmit clock is input within 4 ø...
Page 460 • Reception Receive operation should be stopped (by clearing RE to 0) before making a module stop mode or software standby mode transition. RSR, RDR, and SSR are reset. If a transition is made without stopping operation, the data being received will be invalid. To continue receiving without changing the reception mode after the relevant mode is cleared, set RE to 1 before starting reception.
Page 461 Transition Exit from End of to software software standby Start of transmission transmission standby TE bit Port input/output SCK output pin TxD output pin Port input/output High output Start Stop Port input/output High output SCI TxD Port Port SCI TxD output output Figure 11-24 Asynchronous Transmission Using Internal Clock Transition...
Page 462 <Reception> Read RDRF flag in SSR [1] Receive data being received RDRF = 1 becomes invalid. Read receive data in RDR RE = 0 Transition to software [2] Includes module stop mode. standby mode, etc. Exit from software standby mode, etc. Change operating mode? Initialization...
Page 463: Section 12 Smart Card Interface
Switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting. 12.1.1 Features Features of the smart card interface supported by the H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series are as follows. • Asynchronous mode  Data length: 8 bits ...
Page 464: Block Diagram
12.1.2 Block Diagram Figure 12-1 shows a block diagram of the smart card interface. Internal Module data bus data bus SCMR ø ø/4 Baud rate generator ø/16 Transmission/ ø/64 reception control Parity generation Clock Parity check Legend SCMR : Smart card mode register : Receive shift register : Receive data register : Transmit shift register...
Page 465 12.1.3 Pin Configuration Table 12-1 shows the smart card interface pin configuration. Table 12-1 Smart Card Interface Pins Channel* Pin Name Symbol Function Serial clock pin 0 SCK0 SCI0 clock input/output Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output...
Page 466 12.1.4 Register Configuration Table 12-2 shows the registers used by the smart card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 11, Serial Communication Interface. Table 12-2 Smart Card Interface Registers Channel* Name...
Page 467: Register Descriptions
12.2 Register Descriptions Registers added with the smart card interface and bits for which the function changes are described here. 12.2.1 Smart Card Mode Register (SCMR) — — — — SDIR SINV — SMIF Initial value : — — — —...
Page 468: Serial Status Register (Ssr)
Bit 1—Reserved: Read-only bit, always read as 1. Bit 0—Smart Card Interface Mode Select (SMIF): Enables or disables the smart card interface function. Bit 0 SMIF Description Smart card interface function is disabled (Initial value) Smart card interface function is enabled 12.2.2 Serial Status Register (SSR) TDRE...
Page 469 Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 11.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below. Bit 2 TEND Description [Clearing conditions] •...
Page 470 Bit 7 Description Normal smart card interface mode operation (Initial value) • TEND flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit • Clock output on/off control only GSM mode smart card interface mode operation •...
Page 471: Serial Control Register (Scr)
12.2.4 Serial Control Register (SCR) MPIE TEIE CKE1 CKE0 Initial value : In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2—Operate in the same way as for the normal SCI.
Page 472: Operation
12.3 Operation 12.3.1 Overview The main functions of the smart card interface are as follows. • One frame consists of 8-bit data plus a parity bit. • In transmission, a guard time of at least 2 etu (1 etu in block transfer mode) (elementary time unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame.
Page 473 Data line Clock line Rx (port) Reset line H8S/2338 Series, H8S/2328 Series, or IC card H8S/2318 Series Connected equipment Figure 12-2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed...
Page 474: Data Format
12.3.3 Data Format Normal Transfer Mode: Figure 12-3 shows the smart card interface data format in the normal transfer mode. In reception in this mode, a parity check is carried out on each frame. If an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested.
Page 475 The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).
Page 476 12.3.4 Register Settings Table 12-3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 12-3 Smart Card Interface Register Settings Register Bit 7 Bit 6...
Page 477 The parity bit is 0, corresponding to state Z, since even parity is stipulated for the smart card. With the H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR...
Page 478: Clock
12.3.5 Clock Only an internal clock generated by the built-in baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1, CKS0, BCP1, and BCP0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 12-5 shows some sample bit rates.
Page 479 The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the smaller error is specified.
Page 480: Data Transfer Operations
12.3.6 Data Transfer Operations Initialization: Before transmitting or receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0.
Page 481 Serial Data Transmission (Except Block Transfer Mode): As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 12-4 shows a flowchart for transmitting, and figure 12-5 shows the relation between a transmit operation and the internal registers.
Page 482 Start Initialization Start of transmission ERS = 0? Error handling TEND = 1? Write data to TDR, and clear TDRE flag in SSR to 0 All data transmitted? ERS = 0? Error handling TEND = 1? Clear TE bit to 0 Figure 12-4 Sample Transmission Flowchart...
Page 483 (shift register) (1) Data write Data 1 (2) Transfer from Data 1 Data 1 ; Data remains in TDR TDR to TSR Data 1 I/O signal line output (3) Serial data output Data 1 In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set...
Page 484 Serial Data Reception (Except Block Transfer Mode): Data reception in smart card mode uses the same processing procedure as for the normal SCI. Figure 12-7 shows an example of the transmission processing flow. [1] Perform smart card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0.
Page 485 With the above processing, interrupt handling or data transfer by the DMAC or DTC is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) request will be generated.
Page 486 Interrupt Operation (Except Block Transfer Mode): There are three interrupt sources in smart card interface mode: transmit-data-empty interrupt (TXI) requests, transmit/receive-error interrupt (ERI) requests, and receive-data-full interrupt (RXI) requests. The transmit-end interrupt (TEI) request is not used in this mode. When the TEND flag in SSR is set to 1, a TXI interrupt request is generated.
Page 487: Operation In Gsm Mode
In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DMAC or DTC activation source, the DMAC or DTC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC or DTC.
Page 488: Operation In Block Transfer Mode
Software standby Normal operation Normal operation [1] [2] [3] [4] [5] [6] [7] Figure 12-9 Clock Halt and Restart Procedure Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential.
Page 489 Receive Data Sampling Timing and Receive Margin in Smart Card Interface Mode: In smart card interface mode, the SCI operates on a base clock with a frequency of 32, 64, 372, or 256 times the transfer rate (determined by bits BCP1 and BCP0). In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization.
Page 490 When D = 0.5 and F = 0, M = (0.5 – 1/2 × 372) × 100% = 49.866% Retransfer Operations (Except Block Transfer Mode): Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. •...
Page 491 interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality is received.
Page 492: Section 13 A/D Converter (8 Analog Input Channel Version)
Section 13 A/D Converter (8 Analog Input Channel Version) 13.1 Overview The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series incorporate a successive- approximations type 10-bit A/D converter that allows up to eight analog input channels to be selected. 13.1.1 Features A/D converter features are listed below •...
Page 493: Block Diagram
• Module stop mode can be set  As the initial setting, A/D converter operation is halted. Register access is enabled by exiting module stop mode. 13.1.2 Block Diagram Figure 13-1 shows a block diagram of the A/D converter. Module data bus Internal data bus 10-bit A/D –...
Page 494 13.1.3 Pin Configuration Table 13-1 summarizes the input pins used by the A/D converter. The AV and AV pins are the power supply pins for the analog block in the A/D converter. The pin is the A/D conversion reference voltage pin. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7).
Page 495: Register Configuration
13.1.4 Register Configuration Table 13-2 summarizes the registers of the A/D converter. Table 13-2 A/D Converter Registers Name Abbreviation Initial Value Address* A/D data register AH ADDRAH H'00 H'FF90 A/D data register AL ADDRAL H'00 H'FF91 A/D data register BH ADDRBH H'00 H'FF92...
Page 496: Register Descriptions
13.2 Register Descriptions 13.2.1 A/D Data Registers A to D (ADDRA to ADDRD) AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — Initial value : There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion.
Page 497: A/D Control/Status Register (Adcsr)
13.2.2 A/D Control/Status Register (ADCSR) ADIE ADST SCAN Initial value : R/(W)* Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows the status of the operation. ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode.
Page 498 Bit 5—A/D Start (ADST): Selects starting or stopping of A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST Description...
Page 499 Group Selection Channel Selection Description Single Mode (SCAN = 0) Scan Mode (SCAN = 1) AN0 (Initial value) AN0, AN1 AN0 to AN2 AN0 to AN3 AN4, AN5 AN4 to AN6 AN4 to AN7 13.2.3 A/D Control Register (ADCR) TRGS1 TRGS0 —...
Page 500: Module Stop Control Register (Mstpcr)
Bits 5, 4, 1, and 0—Reserved: Read-only bits, always read as 1. Bit 3—Clock Select 1 (CKS1): Used together with the CKS bit in ADCSR to set the A/D conversion time. See the description of the CKS bit for details. Bit 2—Channel Select 3 (CH3): Reserved.
Page 501: Interface To Bus Master
13.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP).
Page 502: Operation
13.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 13.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1 by software or by external trigger input.
Page 503 Set* ADIE Set* Set* conversion starts ADST Clear* Clear* State of channel 0 Idle (AN0) State of channel 1 Idle A/D conversion Idle A/D conversion Idle (AN1) State of channel 2 Idle (AN2) State of Idle channel 3 (AN3) ADDRA Read conversion result Read conversion result A/D conversion result 2...
Page 504: Scan Mode (Scan = 1)
13.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software, or by timer or external trigger input, A/D conversion starts on the first channel in the group (AN0).
Page 505 Continuous A/D conversion Clear* Set* ADST Clear* A/D conversion time State of channel 0 Idle Idle A/D conversion 4 Idle A/D conversion 1 (AN0) State of Idle Idle Idle A/D conversion 2 A/D conversion 5 channel 1 (AN1) State of Idle Idle channel 2...
Page 506: Input Sampling And A/D Conversion Time
13.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts conversion. Figure 13-5 shows the A/D conversion timing.
Page 507 Table 13-4 A/D Conversion Time (Single Mode) CKS1 = 0 CKS1 = 1 CKS = 0 CKS = 1 CKS = 0 CKS = 1 Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max A/D conversion —...
Page 508: Interrupts
ø ADTRG Internal trigger signal ADST A/D conversion Figure 13-6 External Trigger Input Timing 13.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC or DMAC can be activated by an ADI interrupt.
Page 509: Usage Notes
13.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins 1. Analog input voltage range The voltage applied to analog input pins ANn during A/D conversion should be in the range ≤...
Page 510 100 Ω AN0 to AN7 0.1 µF Notes: Values are reference values. 10 µF 0.01 µF 2. R : Input impedance Figure 13-7 Example of Analog Input Protection Circuit 10 kΩ AN0 to To A/D converter 20 pF Note: Values are reference values. Figure 13-8 Analog Input Pin Equivalent Circuit...
Page 511 A/D Conversion Precision Definitions: H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series A/D conversion precision definitions are given below. • Resolution The number of A/D converter digital output codes • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 to B'0000000001 (see figure 13-10).
Page 512 Digital output Ideal A/D conversion characteristic Quantization error 1022 1023 1024 1024 1024 1024 Analog input voltage Figure 13-9 A/D Conversion Precision Definitions (1)
Page 513 Figure 13-10 A/D Conversion Precision Definitions (2) Permissible Signal Source Impedance: H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 kΩ or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time;...
Page 514 GND such as AV Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. H8S/2338 Series, A/D converter H8S/2328 Series, or equivalent circuit...
Page 515: Section 14 A/D Converter (12 Analog Input Channel Version)
Section 14 A/D Converter (12 Analog Input Channel Version) 14.1 Overview The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series incorporate a successive- approximations type 10-bit A/D converter that allows up to twelve analog input channels to be selected. 14.1.1 Features A/D converter features are listed below •...
Page 516: Block Diagram
• Module stop mode can be set  As the initial setting, A/D converter operation is halted. Register access is enabled by exiting module stop mode. 14.1.2 Block Diagram Figure 14-1 shows a block diagram of the A/D converter. Module data bus Internal data bus 10-bit A/D –...
Page 517: Pin Configuration
14.1.3 Pin Configuration Table 14-1 summarizes the input pins used by the A/D converter. The AV and AV pins are the power supply pins for the analog block in the A/D converter. The pin is the A/D conversion reference voltage pin. The twelve analog input pins are divided into two channel sets and two groups: channel set 0 (AN0 to AN7), channel set 1 (AN12 to AN15), group 0 (AN0 to AN3), and group 1 (AN4 to AN7, AN12 to AN15).
Page 518: Register Configuration
14.1.4 Register Configuration Table 14-2 summarizes the registers of the A/D converter. Table 14-2 A/D Converter Registers Name Abbreviation Initial Value Address* A/D data register AH ADDRAH H'00 H'FF90 A/D data register AL ADDRAL H'00 H'FF91 A/D data register BH ADDRBH H'00 H'FF92...
Page 519 14.2 Register Descriptions 14.2.1 A/D Data Registers A to D (ADDRA to ADDRD) AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — Initial value : There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion.
Page 520 14.2.2 A/D Control/Status Register (ADCSR) ADIE ADST SCAN Initial value : R/(W)* Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows the status of the operation. ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode.
Page 521 Bit 5—A/D Start (ADST): Selects starting or stopping of A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST Description...
Page 522 Channel Selection Description Single Mode Scan Mode (SCAN = 0) (SCAN = 1) Setting prohibited Setting prohibited AN12 AN12 AN13 AN12, AN13 AN14 AN12 to AN14 AN15 AN12 to AN15 AN0 (Initial value) AN0, AN1 AN0 to AN2 AN0 to AN3 AN4, AN5 AN4 to AN6 AN4 to AN7...
Page 523: Module Stop Control Register (Mstpcr)
Bit 7 Bit 6 TRGS1 TRGS0 Description A/D conversion start by external trigger is disabled (Initial value) A/D conversion start by external trigger (TPU) is enabled A/D conversion start by external trigger (8-bit timer) is enabled A/D conversion start by external trigger pin (ADTRG) is enabled Bits 5, 4, 1, and 0—Reserved: Read-only bits, always read as 1.
Page 524: Interface To Bus Master
14.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP).
Page 525: Operation
14.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 14.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1 by software or by external trigger input.
Page 526 Set* ADIE Set* Set* conversion ADST starts Clear* Clear* State of channel 0 Idle (AN0) State of channel 1 Idle Idle Idle A/D conversion A/D conversion (AN1) State of channel 2 Idle (AN2) State of channel 3 Idle (AN3) ADDRA Read conversion result Read conversion result A/D conversion result 1...
Page 527: Scan Mode (Scan = 1)
14.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software, or by timer or external trigger input, A/D conversion starts on the first channel in the group (AN0).
Page 528 Continuous A/D conversion Clear* Set* ADST Clear* A/D conversion time State of channel 0 Idle Idle A/D conversion 1 A/D conversion 4 Idle (AN0) State of channel 1 Idle Idle Idle A/D conversion 2 A/D conversion 5 (AN1) State of Idle Idle channel 2...
Page 529: Input Sampling And A/D Conversion Time
14.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time t after the ADST bit is set to 1, then starts conversion. Figure 14-5 shows the A/D conversion timing.
Page 530: External Trigger Input Timing
Table 14-4 A/D Conversion Time (Single Mode) CKS1 = 0 CKS1 = 1 CKS = 0 CKS = 1 CKS = 0 CKS = 1 Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max A/D conversion —...
Page 531: Interrupts
ø ADTRG Internal trigger signal ADST A/D conversion Figure 14-6 External Trigger Input Timing 14.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC or DMAC can be activated by an ADI interrupt.
Page 532: Usage Notes
14.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins 1. Analog input voltage range The voltage applied to analog input pins ANn during A/D conversion should be in the range ≤...
Page 533 100 Ω AN0 to AN7, AN12 to AN15 0.1 µF Notes: Values are reference values. 10 µF 0.01 µF 2. R : Input impedance Figure 14-7 Example of Analog Input Protection Circuit 10 kΩ To A/D AN0 to AN7, converter AN12 to AN15 20 pF Note: Values are reference values.
Page 534: Section 15 D/A Converter
15.1 Overview The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series include an 8-bit resolution D/A converter with from two to four analog signal output channels. The number of output channels differs from model to model; please check the reference manual for the relevant model for confirmation.
Page 535: Block Diagram
15.1.2 Block Diagram Figure 15-1 shows a block diagram of the D/A converter. Module data bus Internal data bus 8-bit DA1 (DA3) DA0 (DA2) Control circuit Legend DACR01 (DACR23): D/A control register 01 (D/A control register 23) DADR0 to DADR3 : D/A data registers 0 to 3 Figure 15-1 Block Diagram of D/A Converter...
Page 536: Pin Configuration
15.1.3 Pin Configuration Table 15-1 summarizes the input and output pins of the D/A converter. Table 15-1 Pin Configuration Pin Name Symbol Function Analog power pin Input Analog power source Analog ground pin Input Analog ground and reference voltage Analog output pin 0 Output Channel 0 analog output Analog output pin 1...
Page 537: Register Descriptions
15.2 Register Descriptions 15.2.1 D/A Data Registers 0 to 3 (DADR0 to DADR3) Initial value : DADR0 to DADR3 are 8-bit readable/writable registers that store data for conversion. Whenever output is enabled, the values in DADR0 and DADR1 are converted and output from the analog output pins.
Page 538 Channel 0 and 1 (channel 2 and 3) D/A conversions enabled *: Don’t care If the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip enters software standby mode when D/A conversion is enabled, the D/A output is held and the analog power current is the same as during D/A conversion.
Page 539: Module Stop Control Register (Mstpcr)
15.2.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP10 bit or MSTP4 bit in MSTPCR is set to 1, D/A converter operation stops at the end of the bus cycle and a transition is made to module stop mode.
Page 540: Operation
15.3 Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. D/A conversion is performed continuously while enabled by DACR. If either DADR0 or DADR1 is written to, the new data is immediately converted. The conversion result is output by setting the corresponding DAOE0 or DAOE1 bit to 1.
Page 541 DADR0 DACR01 DADR0 DACR01 write cycle write cycle write cycle write cycle ø Address DADR0 Conversion data 1 Conversion data 2 DAOE0 Conversion Conversion result 2 High-impedance state result 1 DCONV DCONV Legend : D/A conversion time DCONV Figure 15-2 Example of D/A Converter Operation...
Page 542: Section 16 Ram
16.1 Overview The H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series have on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer.
Page 543 16.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 16-1 shows the address and initial value of SYSCR. Table 16-1 RAM Register Name Abbreviation Initial Value Address* System control register SYSCR H'01 H'FF39 Note: * Lower 16 bits of the address. 16.2 Register Descriptions 16.2.1...
Page 544: Operation
16.3 Operation When the RAME bit is set to 1, accesses to addresses H'FFDC00 to H'FFFBFF are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units.
Page 545: Section 17 Rom
, MD , and MD ) and the EAE bit in BCRL. The flash memory version of the H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series can be erased and programmed with a PROM programmer, as well as on-board. 17.1.1 Block Diagram Figure 17-1 shows a block diagram of 256 kbytes of on-chip ROM.
Page 546: Register Configuration
17.1.2 Register Configuration The operating mode of the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip is controlled by the mode pins and the BCRL register. The ROM-related registers are shown in table 17-1. Table 17-1 ROM Registers Register Name...
Page 547: Bus Control Register L (Bcrl)
WAITE Initial value : Enabling or disabling of part of the on-chip ROM area in the H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series can be selected by means of the EAE bit in BCRL. For details of the other bits in BCRL, see section 4.2.5, Bus Control Register L (BCRL).
Page 548 Table 17-2 Operating Modes and ROM (F-ZTAT Version) Mode Pins BCRL Mode Operating Mode On-Chip ROM — — — Advanced expanded mode — Disabled with on-chip ROM disabled Advanced expanded mode with on-chip ROM disabled Advanced expanded mode Enabled with on-chip ROM enabled (256 kbytes)* Enabled (64 kbytes)
Page 549 2. Note that in the mode 10 and mode 11 boot modes, the on-chip ROM that can be used immediately after all flash memory is erased by the boot program is the 64-kbyte area from H'000000 to H'00FFFF. 3. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced expanded mode with on-chip ROM enabled.
Page 550: Overview Of Flash Memory
 User program mode • Automatic bit rate adjustment With data transfer in boot mode, the bit rate of the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip can be automatically adjusted to match the transfer bit rate of the host.
Page 551: Overview
• PROM mode Flash memory can be programmed/erased in PROM mode, using a PROM programmer, as well as in on-board programming mode. 17.4.2 Overview Block Diagram Internal address bus Internal data bus (16 bits) FLMCR1 FLMCR2 Operating FWE pin Bus interface/controller mode Mode pins EBR1...
Page 552: Flash Memory Operating Modes
17.4.3 Flash Memory Operating Modes Mode Transitions: When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, the chip enters one of the operating modes shown in figure 17-3. In user mode, flash memory can be read but not programmed or erased.
Page 553: On-Board Programming Modes
RAM boot program area. Host Host Programming control program New application New application program program H8S/2338 Series, H8S/2328 Series, or H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip H8S/2318 Series chip Boot program Boot program Flash memory Flash memory Boot program area...
Page 554 Host Host Programming/ erase control program New application New application program program H8S/2338 Series, H8S/2328 Series, or H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip H8S/2318 Series chip Boot program Boot program Flash memory Flash memory FWE assessment...
Page 555: Flash Memory Emulation In Ram
17.4.5 Flash Memory Emulation in RAM Reading Overlap RAM Data in User Mode and User Program Mode: Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. Flash memory Overlap RAM Emulation block...
Page 556: Differences Between Boot Mode And User Program Mode
Writing Overlap RAM Data in User Program Mode: When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten.
Page 557: Block Configuration
17.4.7 Block Configuration The flash memory is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. Address H'00000 4 kbytes × 8 32 kbytes 64 kbytes 64 kbytes 64 kbytes Address H'3FFFF Figure 17-8 Flash Memory Block Configuration...
Page 558: Pin Configuration
17.4.8 Pin Configuration The flash memory is controlled by means of the pins shown in table 17-4. Table 17-4 Flash Memory Pins Pin Name Abbreviation Function Reset Input Reset Flash write enable Input Flash program/erase protection by hardware Mode 2 Input Sets MCU operating mode Mode 1...
Page 559: Register Configuration
17.4.9 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 17-5. In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set to 1 in SYSCR2 (except RAMER). Table 17-5 Flash Memory Registers Register Name...
Page 560: Register Descriptions
17.5 Register Descriptions 17.5.1 Flash Memory Control Register 1 (FLMCR1) Initial value : FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'00000 to H'3FFFF is entered by setting SWE to 1 when FWE = 1, then setting the EV or PV bit.
Page 561 Bit 6 Description Writes disabled (Initial value) Writes enabled [Setting condition] When FWE = 1 Bit 5—Erase Setup Bit (ESU): Prepares for a transition to erase mode. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 5 Description Erase setup cleared...
Page 562 Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 Description Program-verify mode cleared (Initial value) Transition to program-verify mode [Setting condition] When FWE = 1 and SWE = 1 Bit 1—Erase (E): Selects erase mode transition or clearing.
Page 563: Flash Memory Control Register 2 (Flmcr2)
17.5.2 Flash Memory Control Register 2 (FLMCR2) FLER — — — — — — — Initial value : — — — — — — — FLMCR2 is an 8-bit register that controls the flash memory operating modes. FLMCR2 is initialized to H'00 by a power-on reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00 and writes are invalid.
Page 564: Erase Block Register 1 (Ebr1)
17.5.3 Erase Block Register 1 (EBR1) EBR1 Initial value : EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the SWE bit in FLMCR1 is not set.
Page 565: System Control Register 2 (Syscr2)
Table 17-6 Flash Memory Erase Blocks Block (Size) Address EB0 (4 kbytes) H'000000 to H'000FFF EB1 (4 kbytes) H'001000 to H'001FFF EB2 (4 kbytes) H'002000 to H'002FFF EB3 (4 kbytes) H'003000 to H'003FFF EB4 (4 kbytes) H'004000 to H'004FFF EB5 (4 kbytes) H'005000 to H'005FFF EB6 (4 kbytes) H'006000 to H'006FFF...
Page 566: Ram Emulation Register (Ramer)
Bit 3 FLSHE Description Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB (Initial value) Flash control registers are selected for addresses H'FFFFC8 to H'FFFFCB Bits 2 to 0—Reserved: Read-only bits, always read as 0. 17.5.6 RAM Emulation Register (RAMER) —...
Page 567: On-Board Programming Modes
Bits 2 to 0—Flash Memory Area Selection (RAM2 to RAM0): These bits are used together with bit 3 to select the flash memory area to be overlapped with RAM. (See table 17-7.) Table 17-7 Flash Memory Area Divisions RAM Area Block Name RAMS RAM2...
Page 568: Boot Mode
The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip’s pins have been set to boot mode, the boot program built into the chip is started and the programming control program prepared in the host is serially transmitted to the chip via the SCI.
Page 569 Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Host transmits number Chip measures low period of programming control program of H'00 data transmitted by host bytes (N), upper byte followed by lower byte Chip calculates bit rate and sets value in bit rate register...
Page 570 Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment.
Page 571 On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2-kbyte area from H'FFDC00 to H'FFE3FF is reserved for use by the boot program, as shown in figure 17-12. The area to which the programming control program is transferred is H'FFE400 to H'FFFBFF. The boot program area can be used when the programming control program transferred into RAM enters the execution state.
Page 572: User Program Mode
• Before branching to the programming control program (RAM area H'FFE400 to H'FFFBFF), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1, P31DR = 1).
Page 573 The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip RAM or external memory. Figure 17-13 shows the procedure for executing the program/erase control program when transferred to on-chip RAM.
Page 574: Programming/Erasing Flash Memory
17.7 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made for addresses H'00000 to H'3FFFF by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1.
Page 575: Program-Verify Mode
17.7.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. After the elapse of a given programming time, the programming mode is exited (the P bit in FLMCR1 is cleared to 0, then the PSU bit is cleared to 0 at least (α) µs later).
Page 576 Write pulse application subroutine Start of programming Perform programming in the erased state. Sub-routine write pulse Start Do not perform additional programming Enable WDT Set SWE bit in FLMCR1 on previously programmed addresses. Wait (x) µs Set PSU bit in FLMCR1 Wait (y) µs Store 128-byte program data in program data area and reprogram data area...
Page 577: Erase Mode
17.7.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 17-15. For the wait times (x, y, z, α, ß, γ, ε, η) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N), see the Flash Memory Characteristics section in the reference manual for the relevant model.
Page 578 Start Set SWE bit in FLMCR1 Wait (x) µs n = 1 Set EBR1, EBR2 Enable WDT Set ESU bit in FLMCR1 Wait (y) µs Start of erase Set E bit in FLMCR1 Wait (z) ms n ← n + 1 Clear E bit in FLMCR1 Halt erase Wait (α) µs...
Page 579: Flash Memory Protection
17.8 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 17.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2) are reset.
Page 580: Error Protection
Table 17-11 Software Protection Functions Item Description Program Erase • SWE bit protection Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for area H'00000 to H'3FFFF (Execute in on-chip RAM or external memory.) • Block specification —...
Page 581 Error protection is released only by a reset and in hardware standby mode. Figure 17-16 shows the flash memory state transition diagram. Normal operating mode Reset or hardware standby Program mode RES = 0 or STBY = 0 (hardware protection) Erase mode RD VF PR ER RD VF PR ER...
Page 582: Flash Memory Emulation In Ram
17.9 Flash Memory Emulation in RAM 17.9.1 Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time.
Page 583: Ram Overlap
17.9.2 RAM Overlap An example in which flash memory block area EB1 is overlapped is shown below. This area can be accessed from both the RAM area and flash memory area H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 H'FFDC00 H'FFEBFF Flash memory...
Page 584: Interrupt Handling When Programming/Erasing Flash Memory
2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 includes the vector table. When performing RAM emulation, the vector table is needed by the overlap RAM. 17.10 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including NMI input, are disabled when flash memory is being programmed or...
Page 585: Flash Memory Prom Mode
Programs and data can be written and erased in PROM mode as well as in the on-board programming modes. In PROM mode, the on-chip ROM can be freely programmed using a PROM programmer that supports the Hitachi microcomputer device type with 256-kbyte on-chip flash memory (FZTAT256V3A). Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type.
Page 586: 17.11.2 Socket Adapters And Memory Map
17.11.2 Socket Adapters and Memory Map In PROM mode, a socket adapter is connected to the chip as shown in figures 17-20 and 17-21. Figure 17-19 shows the on-chip ROM memory map and figures 17-20 and 17-21 show the socket adapter pin assignments.
Page 587 H8S/2338F HN27C4096HG (40 Pins) Socket Adapter (40-Pin Conversion) FP-144 Pin No. Pin Name Pin Name 1, 40 3, 36, 39, 61, 64, 89, 90, 91, 96, 11, 30 113, 114 5, 6, 7 9, 18, 27, 37, 38, 47, 56, 71, 81, 94, 123, 124, 135, 136, 137 Legend FWE:...
Page 588 H8S/2328F HN27C4096HG (40 Pins) Socket Adapter (40-Pin Conversion) TFP-120 FP-128 Pin No. Pin Name Pin Name 1, 40 1, 30, 33, 52, 55,74, 5, 34, 39, 58, 61, 82, 75, 76, 81, 93, 94 83, 84, 89, 103, 104 11, 30 5, 6, 7 6, 15, 24, 31, 32, 38, 3, 10, 19, 28, 35, 36,...
Page 589: 17.11.3 Prom Mode Operation
17.11.3 PROM Mode Operation Table 17-13 shows how the different operating modes are set when using PROM mode, and table 17-14 lists the commands used in PROM mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time.
Page 590: 17.11.4 Memory Read Mode
Table 17-14 PROM Mode Commands 1st Cycle 2nd Cycle Number Command Name of Cycles Mode Address Data Mode Address Data Memory read mode 1 + n Write H'00 Read Dout Auto-program mode Write H'40 Write Auto-erase mode Write H'20 Write H'20 Status read mode Write...
Page 591 Command write Memory read mode to A Address stable nxtc Data H'00 Data Note: Data is latched at the rising edge of WE. Figure 17-22 Memory Read Mode Timing Waveforms after Command Write Table 17-16 AC Characteristics when Entering Another Mode from Memory Read Mode = 3.3 V ±0.3 V, V = 25°C ±5°C) (Conditions: V...
Page 592 Other mode command write Memory read mode to A Address stable nxtc to I/O Note: Do not enable WE and OE at the same time. Figure 17-23 Timing Waveforms when Entering Another Mode from Memory Read Mode Table 17-17 AC Characteristics in Memory Read Mode = 3.3 V ±0.3 V, V = 25°C ±5°C) (Conditions: V...
Page 593 Address stable Address stable to A to I/O Figure 17-25 Timing Waveforms for CE/OE Clocked Read 17.11.5 Auto-Program Mode • In auto-program mode, 128 bytes are programmed simultaneously. For this purpose, 128 consecutive byte data transfers should be performed. • A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
Page 594 AC Characteristics Table 17-18 AC Characteristics in Auto-Program Mode = 3.3 V ±0.3 V, V = 25°C ±5°C) (Conditions: V = 0 V, T Item Symbol Unit Notes µs Command write cycle nxtc CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time...
Page 595 17.11.6 Auto-Erase Mode • Auto-erase mode supports only total memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking I/O . Alternatively, status read mode can also be used for this purpose (the I/O7 status polling pin is used to identify the end of an auto-erase operation).
Page 596 to A nxtc nxtc ests erase Erase end identifi- cation signal Erase normal end confirmation signal H'00 H'20 H'20 to I/O Figure 17-27 Auto-Erase Mode Timing Waveforms 17.11.7 Status Read Mode • Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode.
Page 597: 17.11.8 Status Polling
to A nxtc nxtc nxtc H'71 H'71 to I/O Note: I/O to I/O are undefined. Figure 17-28 Status Read Mode Timing Waveforms Table 17-21 Status Read Mode Return Commands Pin Name I/O Attribute Normal Command Program- Erase — — Program- Effective error ming error...
Page 598: 17.11.9 Prom Mode Transition Time
Notes: 1. The flash memory is initially in the erased state when the device is shipped by Hitachi. For other chips for which the erasure history is unknown, it is recommended that auto- erasing be executed to check and supplement the initialization (erase) level.
Page 599: Flash Memory Programming And Erasing Precautions
Use a PROM programmer that supports the Hitachi microcomputer device type with 256-kbyte on-chip flash memory (FZTAT256V3A). Do not select the HN27C4096 setting for the PROM programmer, and only use the specified socket adapter.
Page 600 Do not apply a constant high level to the FWE pin: Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc.
Page 601 Programming/ erasing Wait time: 10 µs possible Wait time: x ø Min 0 µs OSC1 Min 0 µs to MD SWE set SWE cleared SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit) Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
Page 602 Programming/ erasing Wait time: 100 µs possible Wait time: x ø Min 0 µs OSC1 to MD SWE set SWE cleared SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit) Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
Page 603 ø OSC1 Min 0 µs to MD RESW cleared SWE1 bit Mode Boot Mode User User program mode User User program change mode change mode mode mode Period during which flash memory access is prohibited (x: Wait time after setting SWE bit) Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
Page 604: Section 18 Clock Pulse Generator
In the H8S/2338 Series, H8S/2328 Series, and H8S/2318 Series, the CPG has a medium-speed mode in which the bus master runs on a medium-speed clock and the other supporting modules run on the high-speed clock, and a function that allows the medium-speed mode to be disabled and the clock division ratio to be changed for the entire chip.
Page 605: Register Configuration
18.1.2 Register Configuration The clock pulse generator is controlled by SCKCR. Table 18-1 shows the register configuration. Table 18-1 Clock Pulse Generator Register Name Abbreviation Initial Value Address* System clock control register SCKCR H'00 H'FF3A Note:* Lower 16 bits of the address. 18.2 Register Descriptions 18.2.1...
Page 606 • The division ratio set with bits SCK2 to SCK0 should be selected so as to fall within the guaranteed operation range of clock cycle time t given in the AC timing table in the Electrical Characteristics section. Ensure that ø min = 2 MHz, and the condition ø < 2 MHz does not arise.
Page 607: Oscillator
Description Bit 2 Bit 1 Bit 0 SCK2 SCK1 SCK0 DIV = 0 DIV = 1 Bus master is in high-speed Bus master is in high-speed mode (Initial value) mode (Initial value) Medium-speed clock is ø/2 Clock supplied to entire chip is ø/2 Medium-speed clock is ø/4 Clock supplied to entire chip is ø/4 Medium-speed clock is ø/8...
Page 608 See figure 18-4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Avoid Signal A Signal B H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series XTAL EXTAL...
Page 609: External Clock Input
18.3.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 18-5. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode. EXTAL External clock input XTAL...
Page 610 Table 18-4 External Clock Input Conditions = 2.7 V = 3.0 V to 3.3 V to 3.6 V Test Item Symbol Unit Conditions External clock input — — Figure 18-6 low pulse width External clock input — — high pulse width External clock rise time —...
Page 611: Duty Adjustment Circuit
18.4 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (ø). 18.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate ø/2, ø/4, ø/8, ø/16, and ø/32. 18.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock (ø) or one of the medium-speed...
Page 612: Section 19 Power-Down Modes
CPU and bus master mode, and module stop mode is an on-chip supporting module mode (including bus masters other than the CPU). A combination of these modes can be set. After a reset, the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip is in high-speed mode.
Page 613: Register Configuration
Table 19-1 Operating Modes Modules Operating Transition Clearing Mode Condition Condition Oscillator Registers Registers I/O Ports High speed Control Functions High Function High Function High speed mode register speed speed Medium- Control Functions Medium High/ Function Function High speed speed mode register speed medium...
Page 614: Register Descriptions
19.2 Register Descriptions 19.2.1 Standby Control Register (SBYCR) SSBY STS2 STS1 STS0 — — IRQ37S Initial value : — — SBYCR is an 8-bit readable/writable register that performs software standby mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Page 615 Bit 6 Bit 5 Bit 4 STS2 STS1 STS0 Description Standby time = 8192 states (Initial value) Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states* Note: * Not available in the F-ZTAT version.
Page 616: System Clock Control Register (Sckcr)
19.2.2 System Clock Control Register (SCKCR) PSTOP — — — SCK2 SCK1 SCK0 Initial value : — — SCKCR is an 8-bit readable/writable register that controls ø clock output, the medium-speed mode in which the bus master runs on a medium-speed clock and the other supporting modules run on the high-speed clock, and a function that allows the medium-speed mode to be disabled and the clock division ratio to be changed for the entire chip.
Page 617 • The division ratio can be changed while the chip is operating. The clock output from the ø pin will also change when the division ratio is changed. The frequency of the clock output from the ø pin in this case will be as follows: ø...
Page 618: Module Stop Control Register (Mstpcr)
19.2.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode.
Page 619: Medium-Speed Mode
19.3 Medium-Speed Mode When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to medium- speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (ø/2, ø/4, ø/8, ø/16, or ø/32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (the DMAC and DTC) also operate in medium-speed mode.
Page 620: Sleep Mode
19.4 Sleep Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers are retained. Other supporting modules do not stop. Sleep mode is cleared by a reset or any interrupt, and the CPU returns to the normal program execution state via the exception handling state.
Page 621: Usage Notes
Table 19-3 MSTP Bits and Corresponding On-Chip Supporting Modules Register Module MSTPCRH MSTP15 DMA controller (DMAC) MSTP14 Data transfer controller (DTC) MSTP13 16-bit timer-pulse unit (TPU) MSTP12 8-bit timer module MSTP11 Programmable pulse generator (PPG) MSTP10 D/A converter (channels 0 and 1) MSTP9 A/D converter MSTP8...
Page 622: Software Standby Mode
Clearing with the RES Pin: When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip. Note that the RES pin must be held low until clock oscillation stabilizes.
Page 623: Setting Oscillation Stabilization Time After Clearing Software Standby Mode
19.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time).
Page 624: Usage Notes
Software standby mode is then cleared at the rising edge on the NMI pin. Oscillator ø NMIEG SSBY NMI exception Software standby mode NMI exception Oscillation handling (power-down mode) handling stabilization NMIEG=1 time t SSBY=1 OSC2 SLEEP instruction Figure 19-2 Software Standby Mode Application Example 19.6.5 Usage Notes I/O Port Status: In software standby mode, I/O port states are retained.
Page 625: Hardware Standby Mode
Do not change the state of the mode pins (MD to MD ) while the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series chip is in hardware standby mode. Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started.
Page 626: Clock Output Disabling Function
Oscillator STBY Oscillation Reset stabilization exception time handling Figure 19-3 Hardware Standby Mode Timing 19.8 ø Clock Output Disabling Function Output of the ø clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port.
Page 627: Appendix A Instruction Set
Notes: 1. General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). 2. The MAC register cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series.
Page 628 Condition Code Notation Symbol Changes according to the result of the instruction Undetermined (no guaranteed value) Always cleared to 0 Always set to 1 — Not affected by execution of the instruction...
Page 629 Table A-1 Instruction Set (1) Data Transfer Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States* Advanced Mnemonic Operation I H N Z V C #xx:8→Rd8 — — 0 — MOV.B #xx:8,Rd Rs8→Rd8 — — 0 — MOV.B Rs,Rd @ERs→Rd8 —...
Page 630 Table A-1 Instruction Set (cont) (1) Data Transfer Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States* Advanced Mnemonic Operation I H N Z V C @(d:16,ERs)→Rd16 — — 0 — MOV.W @(d:16,ERs),Rd @(d:32,ERs)→Rd16 — — 0 — MOV.W @(d:32,ERs),Rd @ERs→Rd16,ERs32+2→ERs32 —...
Page 631 — — — — — — 7/9/11 [1] STM (ERm-ERn),@-SP Repeated for each register saved Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series MOVFPE MOVFPE @aa:16,Rd Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series...
Page 632 Table A-1 Instruction Set (2) Arithmetic Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States* Advanced Mnemonic Operation I H N Z V C Rd8+#xx:8→Rd8 — ADD.B #xx:8,Rd Rd8+Rs8→Rd8 — ADD.B Rs,Rd Rd16+#xx:16→Rd16 — [3] ADD.W #xx:16,Rd Rd16+Rs16→Rd16 —...
Page 633 Table A-1 Instruction Set (cont) (2) Arithmetic Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States* Advanced Mnemonic Operation I H N Z V C Rd16-Rs16→Rd16 — [3] SUB.W Rs,Rd ERd32-#xx:32→ERd32 — [4] SUB.L #xx:32,ERd ERd32-ERs32→ERd32 — [4] SUB.L ERs,ERd Rd8-#xx:8-C→Rd8 —...
Page 634 Table A-1 Instruction Set (cont) (2) Arithmetic Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States* Advanced Mnemonic Operation I H N Z V C Rd16÷Rs8→Rd16 (RdH: remainder, — — [6] [7] — — DIVXU DIVXU.B Rs,Rd RdL: quotient) (unsigned division) ERd32÷Rs16→ERd32 (Ed: remainder, —...
Page 635 (<bits 31 to 16> of ERd32) TAS @ERd @ERd-0→CCR set, (1)→ — — 0 — (<bit 7> of @ERd) Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series MAC @ERn+, @ERm+ CLRMAC CLRMAC LDMAC LDMAC ERs,MACH LDMAC ERs,MACL...
Page 636 Table A-1 Instruction Set (3) Logical Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States* Advanced Mnemonic Operation I H N Z V C Rd8∧#xx:8→Rd8 — — 0 — AND.B #xx:8,Rd Rd8∧Rs8→Rd8 — — 0 — AND.B Rs,Rd Rd16∧#xx:16→Rd16 —...
Page 637 Table A-1 Instruction Set (4) Shift Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States* Advanced Mnemonic Operation I H N Z V C — — SHAL SHAL.B Rd — — SHAL.B #2,Rd — — SHAL.W Rd — — SHAL.W #2,Rd —...
Page 638 Table A-1 Instruction Set (cont) (4) Shift Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States* Advanced Mnemonic Operation I H N Z V C — — — 0 SHLR SHLR.B Rd — — — 0 SHLR.B #2,Rd —...
Page 639 Table A-1 Instruction Set (cont) (4) Shift Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States* Advanced Mnemonic Operation I H N Z V C — — ROTL ROTL.B Rd — — ROTL.B #2,Rd — — ROTL.W Rd —...
Page 640 Table A-1 Instruction Set (5) Bit-Manipulation Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States* Advanced Mnemonic Operation I H N Z V C (#xx:3 of Rd8)←1 — — — — — — BSET BSET #xx:3,Rd (#xx:3 of @ERd)←1 —...
Page 641 Table A-1 Instruction Set (cont) (5) Bit-Manipulation Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States* Advanced Mnemonic Operation I H N Z V C (Rn8 of @aa:32)←0 — — — — — — BCLR BCLR Rn,@aa:32 (#xx:3 of Rd8)←[¬...
Page 642 Table A-1 Instruction Set (cont) (5) Bit-Manipulation Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States* Advanced Mnemonic Operation I H N Z V C ¬ (#xx:3 of @aa:32)→Z — — — — — BTST BTST #xx:3,@aa:32 ¬...
Page 643 Table A-1 Instruction Set (cont) (5) Bit-Manipulation Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States* Advanced Mnemonic Operation I H N Z V C C→(#xx:3 of @aa:16) — — — — — — BST #xx:3,@aa:16 C→(#xx:3 of @aa:32) —...
Page 644 Table A-1 Instruction Set (cont) (5) Bit-Manipulation Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States* Advanced Mnemonic Operation I H N Z V C C∨(#xx:3 of @aa:8)→C — — — — — BOR #xx:3,@aa:8 C∨(#xx:3 of @aa:16)→C —...
Page 645 Table A-1 Instruction Set (6) Branch Instructions Addressing Mode/ Instruction Length (Bytes) Operation Condition Code No. of States* Branching Condition Advanced Mnemonic I H N Z V C Always — — — — — — BRA d:8(BT d:8) — if condition is true then —...
Page 646 Table A-1 Instruction Set (cont) (6) Branch Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operation Condition Code No. of States* Branching Condition Advanced Mnemonic I H N Z V C — — — — — — BVS d:8 — — — — — — — BVS d:16 —...
Page 647 Table A-1 Instruction Set (cont) (6) Branch Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States* Advanced Mnemonic Operation I H N Z V C PC←ERn — — — — — — JMP @ERn — PC←aa:24 — — — — — — JMP @aa:24 —...
Page 648 Table A-1 Instruction Set (7) System Control Instructions Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States* Advanced Mnemonic Operation I H N Z V C PC→@-SP,CCR→@-SP, 1 — — — — — 8 [9] TRAPA TRAPA #xx:2 — EXR→@-SP,<vector>→PC EXR←@SP+,CCR←@SP+, 5 [9]...
Page 649 Table A-1 Instruction Set (cont) (7) System Control Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Condition Code No. of States* Advanced Operation I H N Z V C Mnemonic CCR→Rd8 — — — — — — STC CCR,Rd EXR→Rd8 — — — — — — STC EXR,Rd CCR→@ERd —...
Page 650 [1] Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. [2] Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series. [3] Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
Page 651: Instruction Codes
Instruction Codes Table A-2 shows the instruction codes.
Page 652 Table A-2 Instruction Codes Instruction Format Instruc- Mnemonic Size tion 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDS #1,ERd...
Page 653 Table A-2 Instruction Codes (cont) Instruction Format Instruc- Mnemonic Size tion 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte BHI d:8 — disp disp BHI d:16 — BLS d:8 —...
Page 654 Table A-2 Instruction Codes (cont) Instruction Format Instruc- Mnemonic Size tion 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd...
Page 655 Table A-2 Instruction Codes (cont) Instruction Format Instruc- Mnemonic Size tion 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd...
Page 656 Table A-2 Instruction Codes (cont) Instruction Format Instruc- Mnemonic Size tion 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,Rd BSET #xx:3,@ERd...
Page 657 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 0 IMM BXOR #xx:3,@aa:32 0 IMM Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series CLRMAC CLRMAC — CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd...
Page 658 Table A-2 Instruction Codes (cont) Instruction Format Instruc- Mnemonic Size tion 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC.B Rd INC.W #1,Rd INC.W #2,Rd...
Page 659 LDM.L @SP+, (ERn-ERn+1) ern+1 LDM.L @SP+, (ERn-ERn+2) ern+2 LDM.L @SP+, (ERn-ERn+3) ern+3 LDMAC LDMAC ERs,MACH Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series LDMAC ERs,MACL MAC @ERn+,@ERm+ — MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd disp MOV.B @(d:32,ERs),Rd...
Page 660 MOV.L ERs,@(d:16,ERd) disp MOV.L ERs,@(d:32,ERd)* disp MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVFPE @aa:16,Rd Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series MOVTPE MOVTPE Rs,@aa:16 MULXS MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd...
Page 661 Table A-2 Instruction Codes (cont) Instruction Format Instruc- Mnemonic Size tion 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte NEG.B Rd NEG.W Rd NEG.L ERd — NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd...
Page 662 Table A-2 Instruction Codes (cont) Instruction Format Instruc- Mnemonic Size tion 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte ROTR ROTR.B Rd ROTR.B #2, Rd ROTR.W Rd ROTR.W #2, Rd ROTR.L ERd ROTR.L #2, ERd ROTXL...
Page 663 Table A-2 Instruction Codes (cont) Instruction Format Instruc- Mnemonic Size tion 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte SHAR SHAR.B Rd SHAR.B #2, Rd SHAR.W Rd SHAR.W #2, Rd SHAR.L ERd SHAR.L #2, ERd SHLL...
Page 664 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM.L(ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC STMAC MACH,ERd Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS...
Page 665 Table A-2 Instruction Codes (cont) Instruction Format Instruc- Mnemonic Size tion 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte XORC XORC #xx:8,CCR XORC #xx:8,EXR Note: Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0. Legend IMM: Immediate data (2, 3, 8, 16, or 32 bits)
Page 666: Operation Code Map
Operation Code Map Table A-3 shows the operation code map.
Page 667 ROTXL ROTL ROTL ROTL ROTXL ROTXL ROTXR ROTXR ROTXR ROTR ROTR ROTR EXTU EXTU EXTS EXTS SUBS SUBS Table Table MOVFPE * MOVTPE * A.3(4) A.3(4) Note: * Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series.
Page 668 Table A-3 Operation Code Map (3) Instruction code 1st byte 2nd byte 3rd byte 4th byte Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. AH AL BH BL CH 01C05 MULXS MULXS 01D05...
Page 669 Table A-3 Operation Code Map (4) Instruction code 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte Instruction when most significant bit of FH is 0. Instruction when most significant bit of FH is 1. AHALBHBLCHCLDHDLEH 6A10aaaa6* BTST BXOR BAND...
Page 670: Number Of States Required For Instruction Execution
Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A-5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A-4 indicates the number of states required for each cycle.
Page 671 Table A-4 Number of States per Cycle Access Conditions External Device On-Chip Supporting Module 8-Bit Bus 16-Bit Bus On-Chip 8-Bit 16-Bit 2-State 3-State 2-State 3-State Cycle Memory Access Access Access Access Instruction fetch 6 + 2m 3 + m Branch address read S Stack operation Byte data access 3 + m...
Page 672 Table A-5 Number of Cycles in Instruction Execution Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDS #1/2/4,ERd ADDX ADDX #xx:8,Rd ADDX Rs,Rd...
Page 673 Table A-5 Number of Cycles in Instruction Execution (cont) Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16...
Page 674 Table A-5 Number of Cycles in Instruction Execution (cont) Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16...
Page 675 Table A-5 Number of Cycles in Instruction Execution (cont) Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32...
Page 676 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CLRMAC Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd...
Page 677 Table A-5 Number of Cycles in Instruction Execution (cont) Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic EEPMOV EEPMOV.B 2n+2* EEPMOV.W 2n+2* EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd...
Page 678 (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACH Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series LDMAC ERs,MACL MAC @ERn+,@ERm+ Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series MOV.B #xx:8,Rd MOV.B Rs,Rd...
Page 679 MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVFPE @:aa:16,Rd Can not be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series MOVTPE MOVTPE Rs,@:aa:16 MULXS MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd...
Page 680 Table A-5 Number of Cycles in Instruction Execution (cont) Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn...
Page 681 Table A-5 Number of Cycles in Instruction Execution (cont) Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd 2/3* Advanced SHAL SHAL.B Rd...
Page 682 STC.W EXR,@aa:32 STM.L (ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC STMAC MACH,ERd Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBS #1/2/4,ERd...
Page 683 Table A-5 Number of Cycles in Instruction Execution (cont) Branch Byte Word Instruction Address Stack Data Data Internal Fetch Read Operation Access Access Operation Instruction Mnemonic XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR XORC #xx:8,EXR Notes: 1.
Page 684: Bus States During Instruction Execution
Bus States During Instruction Execution Table A-6 indicates the types of cycles that occur during instruction execution by the CPU. See table A-4 for the number of states per cycle. How to Read the Table: Order of execution Instruction Internal operation, JMP@aa:24 R:W 2nd R:W EA...
Page 685 Figure A-1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. ø Address bus HWR, LWR High Internal R:W 2nd R:W EA operation...
Page 686 Table A-6 Instruction Execution Cycles Instruction ADD.B #xx:8,Rd R:W NEXT ADD.B Rs,Rd R:W NEXT ADD.W #xx:16,Rd R:W 2nd R:W NEXT ADD.W Rs,Rd R:W NEXT ADD.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT ADD.L ERs,ERd R:W NEXT ADDS #1/2/4,ERd R:W NEXT ADDX #xx:8,Rd R:W NEXT ADDX Rs,Rd...
Page 687 Table A-6 Instruction Execution Cycles (cont) Instruction BLE d:8 R:W NEXT R:W EA BRA d:16 (BT d:16) R:W 2nd Internal operation, R:W EA 1 state BRN d:16 (BF d:16) R:W 2nd Internal operation, R:W EA 1 state BHI d:16 R:W 2nd Internal operation, R:W EA 1 state BLS d:16...
Page 688 Table A-6 Instruction Execution Cycles (cont) Instruction BCLR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B:M EA R:W:M NEXT W:B EA BCLR Rn,Rd R:W NEXT BCLR Rn,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR Rn,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BCLR Rn,@aa:16 R:W 2nd...
Page 689 Table A-6 Instruction Execution Cycles (cont) Instruction BNOT #xx:3,@ERd R:W 2nd R:B:M EA R:W:M NEXT W:B EA BNOT #xx:3,@aa:8 R:W 2nd R:B:M EA R:W:M NEXT W:B EA BNOT #xx:3,@aa:16 R:W 2nd R:W 3rd R:B:M EA R:W:M NEXT W:B EA BNOT #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th...
Page 690 R:W:M NEXT BXOR #xx:3,@aa:32 R:W 2nd R:W 3rd R:W 4th R:B EA R:W:M NEXT CLRMAC Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series CMP.B #xx:8,Rd R:W NEXT CMP.B Rs,Rd R:W NEXT CMP.W #xx:16,Rd R:W 2nd R:W NEXT CMP.W Rs,Rd...
Page 691 Table A-6 Instruction Execution Cycles (cont) Instruction INC.W #1/2,Rd R:W NEXT INC.L #1/2,ERd R:W NEXT JMP @ERn R:W NEXT R:W EA JMP @aa:24 R:W 2nd Internal operation, R:W EA 1 state JMP @@aa:8 Advanced R:W NEXT R:W:M aa:8 R:W aa:8 Internal operation, R:W EA 1 state JSR @ERn...
Page 692 R:W 2nd R:W NEXT Internal operation, R:W:M stack (H) R:W stack (L) 1 state LDMAC ERs,MACH Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series LDMAC ERs,MACL MAC @ERn+,@ERm+ MOV.B #xx:8,Rd R:W NEXT MOV.B Rs,Rd R:W NEXT MOV.B @ERs,Rd...
Page 693 R:W 2nd R:W:M 3rd R:W 4th R:W NEXT W:W:M EA W:W EA+2 MOVFPE @aa:16,Rd Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series MOVTPE Rs,@aa:16 MULXS.B Rs,Rd R:W 2nd R:W NEXT Internal operation, 11 states MULXS.W Rs,ERd...
Page 694 Table A-6 Instruction Execution Cycles (cont) Instruction OR.W #xx:16,Rd R:W 2nd R:W NEXT OR.W Rs,Rd R:W NEXT OR.L #xx:32,ERd R:W 2nd R:W 3rd R:W NEXT OR.L ERs,ERd R:W 2nd R:W NEXT ORC #xx:8,CCR R:W NEXT ORC #xx:8,EXR R:W 2nd R:W NEXT POP.W Rn R:W NEXT Internal operation, R:W EA...
Page 695 Table A-6 Instruction Execution Cycles (cont) Instruction ROTXR.L #2,ERd R:W NEXT R:W NEXT R:W stack (EXR) R:W stack (H) R:W stack (L) Internal operation, R:W 1 state Advanced R:W NEXT R:W:M stack (H) R:W stack (L) Internal operation, R:W 1 state SHAL.B Rd R:W NEXT SHAL.B #2,Rd...
Page 696 STM.L(ERn–ERn+3),@–SP R:W 2nd R:W:M NEXT Internal operation, W:W:M stack (H) W:W stack (L) 1 state STMAC MACH,ERd Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series STMAC MACL,ERd SUB.B Rs,Rd R:W NEXT SUB.W #xx:16,Rd R:W 2nd R:W NEXT SUB.W Rs,Rd...
Page 697 Table A-6 Instruction Execution Cycles (cont) Instruction XOR.L ERs,ERd R:W 2nd R:W NEXT XORC #xx:8,CCR R:W NEXT XORC #xx:8,EXR R:W 2nd R:W NEXT Reset exception Advanced R:W VEC R:W VEC+2 Internal operation, R:W handling 1 state Interrupt exception Advanced Internal operation, W:W stack (L) W:W stack (H) W:W stack (EXR) R:W:M VEC...
Page 698: Condition Code Modification
Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. 31 for longword operands 15 for word operands 7 for byte operands The i-th bit of the source operand The i-th bit of the destination operand The i-th bit of the result The specified bit in the destination operand...
Page 699 — — — — — Z = Dn BTST — — — — C = C' · Dn + C' · Dn BXOR — — — — CLRMAC Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series...
Page 700 — — — — — — — — — — Stores the corresponding bits of the result. No flags change when the operand is EXR. — — — — — LDMAC Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series...
Page 701 Instruction Definition — — N = Rm Z = Rm · Rm–1 · ..· R0 MOVFPE Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series MOVTPE MULXS — — — N = R2m Z = R2m · R2m–1 · ..· R0 MULXU —...
Page 702 C = D0 (1-bit shift) or C = D1 (2-bit shift) SLEEP — — — — — — — — — — — — — — — STMAC Cannot be used in the H8S/2338 Series, H8S/2328 Series, or H8S/2318 Series...
Page 703 Table A-7 Condition Code Modification (cont) Instruction Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ..· R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm ·...
Page 704: Appendix B Internal I/O Registers
Appendix B Internal I/O Registers Addresses Register Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Width H’F800 16/32* bits H’FBFF CHNE DISEL CHNS — — — —...
Page 705 Register Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Width H’FE90 TCR4 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU4 16 bits H’FE91 TMDR4 — —...
Page 706 Register Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Width H’FEC4 IPRA — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 Interrupt 8 bits controller H’FEC5 IPRB —...
Page 707 Register Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Width H’FEF0 MAR1AH — — — — — — — — DMAC 16 bits H’FEF1 H’FEF2 MAR1AL H’FEF3 H’FEF4 IOAR1A...
Page 708 Register Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Width H’FF2C ISCRH Interrupt 8 bits IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA controller H’FF2D ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA H’FF2E IRQ7E...
Page 709 Register Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Width H’FF53 PORT4 Ports 8 bits H’FF54 PORT5 H’FF55 PORT6 H’FF56 PORT7 — — H’FF57 PORT8 — H’FF58 PORT9 —...
Page 710 Register Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Width H’FF78 SMR0 C/A/ CHR/ STOP/ CKS1 CKS0 SCI0, 8 bits GM * BLK * BCP1 * BCP0 * smart card interface 0...
Page 711 Register Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Width H'FF90 ADDRAH AD9 A/D converter 8 bits H'FF91 ADDRAL AD1 — — — — — — H'FF92 ADDRBH AD9 H'FF93...
Page 712 Register Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Width H’FFC8 * FLMCR1 FWE FLASH 8 bits H’FFC9 * FLMCR2 FLER — — — — — —...
Page 713 Register Data Bus Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Width H’FFF0 TCR2 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU2 16 bits H’FFF1 TMDR2 — —...
Page 714 Publication Date: 1st Edition, March 1999 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Group Hitachi, Ltd. Edited by: Technical Documentation Group UL Media Co., Ltd. Copyright © Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.

This manual is also suitable for:

H8s/2328 series H8s/2318 series