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Csync
HVTH
Digital H separation
counter
SEPH
Figure 27.4 HVTH Value and SEPH Generation Timing
The following shows examples of HVTHR settings.
(HVTHR – 1) × (2/OSC) > 1.6 µs or 3.2 µs
Condition:
System clock OSC = 10 MHz
2/OSC = 5 MHz = 0.2 µs
Example 1: To detect equalizing pulses
Hsync detection threshold value: 1.6 µs
1.6 µs / 0.2 µs = 8
HVTHR value = H'8 (8)
Example 2: To not detect equalizing pulses
Hsync detection threshold value: 3.2 µs
3.2 µs / 0.2 µs = 16
HVTHR value = H'10 (16)
In general, to detect Hsync pulses continuously, set the HVTHR value so that 2.35-µs equalizing
pulses can be detected. However, if an equalizing pulse at an Hsync pulse position is lost in a
weak field, a Hsync-Vsync phase-difference error will occur, and the field will not be detected
correctly. In such a weak field, this error can be prevented by eliminating 2.35-µs equalizing
pulses. Figure 27.5 shows the timing when a phase-difference error occurs.
When Equalizing Pulses Are Not Detected
About
3.2 µs to 2.0 µs
Rev. 1.0, 02/00, page 771 of 1141
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