Hitachi H8S/2199 Hardware Manual page 1024

H'D09D: DVCFG Mask Interval Register CTMR: Frequency Divider
Bit :
Initial value :
R/W :
H'D09E: FG Control Register FGCR: Frequency Divider
Bit :
Initial value :
R/W :
H'D0A0: Servo Port Mode Register SPMR: Servo Port
Bit :
CTLSTOP
Initial value :
R/W
R/W :
CTLSTOP bit
0 CTL circuit operates
1 CTL circuit does not operate
Rev. 1.0, 02/00, page 1022 of 1141
7 6
— — CPM5
1 1
— —
7 6
— —
1 1
— —
7 6
—
CFGCOMP
0 1
R/W
—
CFG input method switch bit
0 Zero cross type comparator method for CFG signal input
1 Digital signal input method for CFG signal input
(Initial value)
5 4
CPM4 CPM3
1 1
W W
5 4
— — —
1 1
— — —
DFG edge select bit
0 NCDFG signal rising edge is selected
1 NCDFG signal falling edge is selected
5 4
—
0 1
—
3 2
CPM2 CPM1
1 1
W W
3 2 1
— —
1 1 1
— —
3 2
— —
1 1
— —
1 0
CPM0
1 1
W W
0
DRF
0
W
(Initial value)
1 0
— —
1 1
— —
(Initial value)