Register Configuration; Register Descriptions; Address Trap Control Register (Atcr) - Hitachi H8S/2199 Hardware Manual

25.1.3

Register Configuration

Table 25.1 Register List
Name
Address trap control register
Trap address register 0
Trap address register 1
Trap address register 2
Note: * Lower 16 bits of the address.
25.2

Register Descriptions

25.2.1

Address Trap Control Register (ATCR)

Bit :
Initial value :
R/W :
Bits 7 to 3    Reserved: These bits cannot be modified and are always read as 1.
Bit 2    Trap Control 2 (TRC2): Sets ON/OFF operation of the address trap function 2.
Bit 2
TRC2 Description
0 Address trap function 2 disabled
1 Address trap function 2 enabled
Rev. 1.0, 02/00, page 532 of 1141
Abbrev.
ATCR
TAR0
TAR1
TAR2
7 6 5
— — —
1 1 1
— — —
R/W Initial Value
R/W H'F8
R/W H'F00000
R/W H'F00000
R/W H'F00000
4 3
— — TRC2
1 1
— —
R/W
Address *
H'FFB9
H'FFB0 to H'FFB2
H'FFB3 to H'FFB5
H'FFB6 to H'FFB8
2 1 0
TRC1 TRC0
0 0 0
R/W R/W
(Initial value)