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Bit 5 DDC Mode Switch Interrupt Enable Bit (IE): Enables or disables an interrupt request to
the CPU when the format for IIC channel 0 is automatically switched.
Bit 5
IE
Description
0
Disables an interrupt at automatic format switching
1
Enables an interrupt at automatic format switching
Bit 4 DDC Mode Switch Interrupt Flag (IF): Indicates the interrupt request to the CPU when
the format for IIC channel 0 is automatically switched.
Bit 4
IF
Description
0
Interrupt has not been requested
[Clearing condition]
When 0 is written after IF = 1 is read
1
Interrupt has been requested
[Setting condition]
When an SCL falling edge is detected when SWE = 1
Bits 3 to 0 IIC Clear 3 to 0 (CLR3 to CLR0): Control the IIC0 and IIC1 initialization. These
are write-only bits and are always read as 1.
Writing to these bits generates a clearing signal for the internal latch circuit which initializes the
IIC status.
The data written to these bits are not held. When initializing the IIC, be sure to use the MOV
instruction to write to all the CLR3 to CLR0 bits at the same time; do not use bit manipulation
instructions such as BCLR.
When reinitializing the module status, the CLR3 to CLR0 bits must be rewritten.
Rev. 1.0, 02/00, page 486 of 1141
(Initial value)
(Initial value)
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