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MB96300 Super Series Hardware Manual
2
21.3
I
C Interface Operation
2
The I
C bus executes communication using two bi-directional bus lines, the serial data
line (SDA) and serial clock line (SCL). The I
SCL) corresponding to these lines, enabling wired logic applications.
■ Start conditions
When the bus is free (BB="0" in IBSR, MSS="0" in IBCR), writing "1" to the MSS bit places the I
interface in master mode and generates a start condition.
If a "1" is written to it while the bus is idle (MSS="0" and BB="0"), a start condition is generated and the
contents of the IDAR register (which should be address data) is sent.
Repeated start conditions can be generated by writing "1" to the SCC bit when in bus master mode and
interrupt status (MSS="1" and INT="1" in IBCR).
If a "1" is written to the MSS bit while the bus is in use (BB="1" and TRX="0" in IBSR; MSS="0"and
INT="0"in IBCR), the interface waits until the bus is free and then starts sending.
If the interface is addressed as slave with write access (data reception) in the meantime, it will start sending
after the transfer ended and the bus is free again. If the interface is sending data as slave in the meantime, it
will not start sending data if the bus is free again. It is important to check whether the interface was addressed
as slave (MSS="0" in IBCR and AAS="1" in IBSR), sent the data byte successfully (MSS="1" in IBCR) or
failed to send the data byte (AL="1" in IBSR) at the next interrupt.
Writing "1" to the MSS bit or SCC bit in any other situation has no significance.
■ Stop conditions
Writing "0" to the MSS bit in master mode (MSS="1" and INT="1" in IBCR) generates a stop condition and
places the device in slave mode. Writing "0" to the MSS bit in any other situation has no significance.
After clearing the MSS bit, the interface tries to generate a stop condition which might fail if a certain
external condition causes signal transition caused from "1" to "0" at the SCL line before the generation of this
stop condition. In this case, the AL bit is set to "1" and interrupt is signaled at the end of the next byte.
■ Slave address detection
In slave mode, after a start condition is generated the BB is set to "1" and data sent from the master device is
received into the IDAR register.
After the reception of eight bits, the contents of the IDAR register is compared to the ISBA register using the
bit mask stored in ISMK if the ENSB bit in the ISMK register is "1". If a match results, the AAS bit is set to
"1" and an acknowledge signal is sent to the master. Then bit 0 of the received data (bit 0 of the IDAR
register) is inverted and stored in the TRX bit.
If the ENTB bit in the ITMK register is "1" and a ten bit address header (11110, TA1, TA0, write access) is
detected, the interface sends an acknowledge signal to the master and stores the inverted last data bit in the
TRX register. No interrupt is generated. Then, the next transferred byte is compared (using the bit mask
stored in ITMK) to the lower byte of the ITBA register. If a match is found, an acknowledge signal is sent to
the master, the AAS bit is set and an interrupt is generated.
If the interface was addressed as slave and detects a repeated start condition, the AAS bit is set after reception
of the ten bit address header (11110, TA1, TA0, read access) and an interrupt is generated.
CHAPTER 21 400 kHz I2C INTERFACE
2
C interface has two open-drain I/O pins (SDA/
2
C
567
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