Fujitsu MB96300 series Hardware Manual page 1029

MB96300 Super Series Hardware Manual
■ Write, data polling, read (CE control)
Third bus cycle
AQ18 to AQ0
WE
OE
CE
DQ7 to DQ0
5.0 V
PA: Write address
PD: Write data
DQ7: Reverse output of write data
D : Output of write data
OUT
Note:
The last two bus cycle sequences out of the four are described.
Figure C-3 Timing diagram for write access (CE control)
7AAAA PA
H
t
WC
t t
AS AH
t
WH
t
GHWL
t
CP
t
CPH
t
WS
t
DH
A0 PD
H
t
DS
APPENDIX C Timing Diagrams in Flash Memory Mode
Data polling
PA
t
WHWH1
D
DQ7
OU
T
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