Fujitsu MB96300 series Hardware Manual page 469

MB96300 Super Series Hardware Manual
0
1
Bit 3: OUT1 (Synchronized output of Alarm Comparator OV output)
0
1
Bit 2: IRQ (Interrupt request)
0
1
Write "0" to IRQ to clear an interrupt request. Writing "1" to IRQ has no effect. "1" is read from this bit
when a read-modify-write instruction is used.
Remark:
When IRQ is cleared at the same time, the Alarm comparator requests an interrupt, the interrupt request has higher
priority and IRQ is set to "1". To clear an interrupt caused by a persistent out of voltage range condition, first
disable the undervoltage and/or overvoltage interrupt generation (OVEN = 0 and/or UVEN = 0), then clear the IRQ
bit separately.
Bit 1: IEN (Interrupt enable)
0
1
Bit 0: PD (Power down)
0
1
Analog input voltage < V
EVTL
analog input voltage < V
IVTL
Analog input voltage > V
EVTL
analog input voltage > V
IVTL
Analog input voltage < V
EVTH
analog input voltage < V
IVTH
Analog input voltage > V
EVTH
analog input voltage > V
IVTH
No under- or overvoltage condition detected
Under- or overvoltage condition detected
Interrupt assertion disabled [Initial value]
Interrupt assertion enabled
Run mode (analog part) [Initial value]
Power down mode (analog part)
CHAPTER 19 ALARM COMPARATOR
when AECSRn:INTREF = 0 or
when AECSRn:INTREF = 1
when AECSRn:INTREF = 0 or
when AECSRn:INTREF = 1
when AECSRn:INTREF = 0 or
when AECSRn:INTREF = 1
when AECSRn:INTREF = 0 or
when AECSRn:INTREF = 1
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