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MB96300 Super Series Hardware Manual
Table 8.5-1 Function Description of Each Bit of the Reset Configuration Register (RCR) (2/3)
Bit name
bit 1
LVRE:
Low Voltage Reset
Enable bit
bit 2
LVDE:
Low Voltage
Detector Enable bit
bit 3
CSDRE:
Clock Stop
Detection Reset
Enable bit
bit 4
MCSDI:
Main Clock Stop
Detection Interval
select bit
• This bit controls the Low voltage reset function which is one reset cause of the Power
reset.
• Setting this bit to "1" enables the Low voltage reset function.
• Writing "0" to this bit disables the function.
• This bit is initialized to "1" (Low voltage reset active) by an External and a Power
(power-on) reset only.
• Do not disable the low voltage detector (by writing "0" to the LVDE bit) as long as
this bit is set to "1".
• Do not set this bit from "0" to "1" before the low voltage detector is enabled and
stabilized.
• In devices in which the low voltage reset circuit is always enabled in the Internal
vector mode, the setting of this bit has no effect for Mode pins set to "011" (Persistent
Low Voltage Reset feature).
• This bit controls the low voltage detector which is used for the Low voltage reset
function.
• Setting this bit to "1" enables the low voltage detector.
• Writing "0" to this bit disables the low voltage detector.
• This bit is initialized to "1" (low voltage detector active) by an External and a Power
(power-on) reset only.
• Do not set this bit to "0" as long as LVRE is set to "1".
• The low voltage detector is enabled by setting this bit to "1". However this circuit
needs a stabilization time after activation as specified in the datasheet. Do not activate
the Low voltage reset function before this time has elapsed.
• In devices in which the low voltage reset circuit is always enabled in the Internal
vector mode, the setting of this bit has no effect for Mode pins set to "011" (Persistent
Low Voltage Reset feature).
• This bit enables the Clock stop detection reset function.
• This bit can only be written when the System clock 1 is set to RC clock.
• Setting this bit to "1" enables the Clock stop detection reset.
• Writing "0" to this bit disables the Clock stop detection reset.
• This bit is initialized to "0" (Clock stop detection reset disabled) by any reset.
• After activation, a Clock stop detection reset is asserted in the following three cases:
1. When a missing Main clock is detected while the Main or PLL clock is selected for
the System clocks CLKS1 or CLKS2 or the Watchdog timer.
2.When a missing Sub clock is detected while the Sub clock is selected for the
System clocks CLKS1 or CLKS2 or the Watchdog timer.
3.When "0" is written to the CKSR: RCE bit to disable the RC oscillator.
• This bit controls the measurement interval of the Main clock stop detection circuit.
• This bit is initialized to "0" by any reset.
• Writing "0" to this bit sets the interval time to 6 - 8 RC clock cycles.
• Writing "1" to this bit sets the interval time to 3 - 4 RC clock cycles.
• The Main clock stop detection circuit sets the Main clock missing flag (RCCSR:
MCMF) if no rising edge of the Main clock input signal (CLKMC) was observed
within the selected interval time.
CHAPTER 8 RESETS AND STARTUP
Function
211
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