Fujitsu MB96300 series Hardware Manual page 341

MB96300 Super Series Hardware Manual
Figure 12.3-10 Non-multiplexed 16-bit bus: One automatic ready wait cycle added (EACL:R[2:0]='001',
ECLK
A[23:16]
A[15:00]
CS1
CS2
UB
LB
ALE
RD
AD[15:08]
AD[07:00]
WR
WRH
WRL
AD[15:08]
AD[07:00]
CLKB
AD
WR
WD
RD
READY
EACL:STS='0', EACL:ACE='0)'
Addr 1 (CS1 area)
Addr 1 (CS1 area)
Write Data 1
Write Data 1
16 bit access
Addr 1 Addr 2
WR 1 WR 2
Write Data 1
CHAPTER 12 EXTERNAL BUS INTERFACE
Addr 2 (CS1 area)
Addr 2 (CS1 area)
RD1
RD1 RD2
undefined data
Write Data 2
8 bit access
(even address)
Addr 3
WR 3
Write Data 2
RD1 RD2
Addr 3 (CS2 area)
Addr 3 (CS2 area)
RD3
Write Data 3
undefined data
8 bit access
(odd address)
Write Data 3
RD3
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