Fujitsu MB96300 series Hardware Manual page 507

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MB96300 Super Series Hardware Manual

Receive interrupt Generation and Flag Set Timing

The following are the receive interrupt causes: completion of reception (SSRn:RDRF) and

occurrence of a reception error (SSRn:PE, ORE, or FRE).

■ Receive interrupt generation and ﬂag set timing

Generally a receive interrupt is generated, if the received data is complete (when ESIRn:AICD = "0":

SSRn:RDRF = "1", when ESIRn:AICD = "1": ESIRn:RDRF = "1") and the receive interrupt Enable (RIE)

flag bit of the Serial Status Register (SSRn) was set to "1". This interrupt is generated if the first stop bit is

detected in mode 0, 1, 2 (if SSM = 1), 3, or the last data bit was read in mode 2 (if SSM = 0).

If a reception error has occurred, the Reception Data Register (RDRn) contains invalid data in each mode.

Receive data

Receive data

Receive data

(if RDRF = "1")

*1: The PE flag will always remain "0" in mode 1 or 3.

*2: ORE only occurs, if the reception data is not read by the CPU (RDRF = 1) and

another data frame is read.

ST: Start Bit

The example in Figure 20.5-1 "Reception operation and flag set timing" does not show all possible

reception options for mode 0 and 3. Here it is: "7p1" and "8N1" (p = "E" [even] or "O" [odd]).

Figure 20.5-1 Reception operation and ﬂag set timing

SP: Stop Bit

A/D: Mode 1 (multi processor) address/data selection bit

reception interrupt occurs

CHAPTER 20 USART