Table of Contents
Advertisement
CHAPTER 33 FLASH MEMORY
■ Flash Memory Timing Configuration register high byte (MFMTCH, SFMTCH)
Figure 33.4-3 Configuration of the Flash Memory Timing Configuration register (MFMTCH, SFMTCH)
Address:
0003F3
("Main" Flash)
H
0003F7
("Satellite" Flash)
H
15
EQL2 EQL1 EQL0
R/W R/W R/W R/W R/W
R/W
: Readable and writable
: Initial value
Table 33.4-3
Bit name
bit 8
ATDINIT:
ATDIN Initial
value
852
14
13
12
11
10
9
ATD-
ATD-
ATDL1 ATDL0
EQD1
EQD0
R/W R/W R/W
• This bit defines the initial value of the ATDIN signal.
• When setting this signal to "0", then ATDIN is parked in the "0" position. It is
asserted to "1" at the beginning of a Flash access (read or write). ATDL must
be set to "01" or higher in this case.
• Setting this bit to "1" parks ATDIN in the "1" position. ATDIN becomes "1"
already at the end of the pervious Flash access.
• This bit is initialized to "0" by any reset.
8
Initial value
ATD-
0 0 0 0 0 0 1 0
INIT
bit8
ATDINIT
0
ATDIN parked in '0' position
1
ATDIN parked in '1' position
bit10
bit9
ATDL1
ATDL0
0
0
ATDIN falling edge at access start
0
1
ATDIN falling edge delayed by 0.5 CLKS1 cycles
1
0
ATDIN falling edge delayed by 1.0 CLKS1 cycles
1
1
ATDIN falling edge delayed by 1.5 CLKS1 cycles
bit12
bit11
ATDEQD1
ATDEQD0
0
0
rising EQIN 0.5 CLKS1 cycles after falling ATDIN
0
1
rising EQIN 1.0 CLKS1 cycles after falling ATDIN
1
0
rising EQIN 1.5 CLKS1 cycles after falling ATDIN
1
1
rising EQIN 2.0 CLKS1 cycles after falling ATDIN
bit15
bit14
bit13
EQL2
EQL1
EQL0
0
0
0
EQIN length is 0.5 CLKS1 cycles
0
0
1
EQIN length is 1.0 CLKS1 cycles
0
1
0
EQIN length is 1.5 CLKS1 cycles
0
1
1
EQIN length is 2.0 CLKS1 cycles
1
0
0
EQIN length is 2.5 CLKS1 cycles
1
0
1
EQIN length is 3.0 CLKS1 cycles
1
1
0
EQIN length is 3.5 CLKS1 cycles
1
1
1
EQIN length is 4.0 CLKS1 cycles
Function
B
ATDIN Initial value
ATDIN length
ATDIN to EQIN delay
EQIN length
Advertisement
Table of Contents
