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CHAPTER 14 16-BIT I/O TIMER
14.3.2
Control Status Register (TCCSLn)
The control status register (TCCSLn) sets the operation mode of the 16-bit Free-Running
Timer, starts and stops the 16-bit Free-Running Timer, and controls interrupts.
■ Control status register of Free-Running Timer (TCCSLn)
Figure 14.3-3 Control status register of Free-Running Timer (TCCSLn)
IVF
R/W R/W R/W R/W R/W
R/W
:
Readable and writable
:
Initial value
370
7
6
5
4
3
2
1
CLR CLK2 CLK1
IVFE
STOP MODE
R/W
R/W R/W
MB96300 Super Series Hardware Manual
TCCSLn
0
Initial value
CLK0
0 0 0 0 0 0 0 0
bit 2
bit1
bit 0
CLK2
CLK1
CLK0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
bit 3
Clear Timer
CLR
Read
0
read always "0"
1
bit 4
Set Reset condition of timer
MODE
0
Initialization by reset or clear bit
1
Init. by reset, clear bit, or compare reg. 0 and 4
bit 5
Stop the timer
STOP
0
Counter enabled
1
Counter disabled (stop)
bit 6
IVFE
Interrupt enable bit
0
Interrupt disabled
1
Interrupt enabled
bit 7
Interrupt request flag bit
IVF
Read
0
No interrupt
1
Interrupt request
B
Count Clock Selection
φ
φ / 2
φ / 4
φ / 8
φ / 16
φ / 32
φ / 64
φ / 128
φ = Peripheral clock CLKP1
Write
no effect
clear timer to "0000"
Write
clear this bit
no effect
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