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MB96300 Super Series Hardware Manual
of the corresponding LCDER register bits is ignored.
When internal divide resistors are selected the external voltage pins can not be connected. The setting of
LCDVER:V[0:3] is ignored
bit4 BK: Select blanking
0
1
bit3-2: Select a display mode
Table 26.2-1 Function Settings
MS1
0
0
1
1
Notes:
•
If the display mode select bit (MS[1:0]) is set to "00", the LCD Controller is disabled, i. e. a "L" level
is output to the common/segment pins.
bit1-0: Frame period
Table 26.2-2 Frame period
FP1
0
0
1
1
•
F
CLKP1
•
F
CL
•
N: Time division number (Selected with the display mode select bits, MS1 and MS0.)
•
Select an appropriate value in accordance with the frame frequency of your LCD panel.
■ LCD Common Pin switching Register (LCDCMR)
Enable LCD display
Disable (blank) LCD display
MS0
0
Deactivate LCD
1
1/2 duty cycle output mode (Time division number: N=2, COM0-COM1)
0
1/3 duty cycle output mode (Time division number: N=3, COM0-COM2)
1
1/4 duty cycle output mode (Time division number: N=4, COM0-COM3)
FP0
When peripheral clock CLKP1
is selected:
13
0
F
/(2
X N)
CLKP1
15
1
F
/(2
X N)
CLKP1
17
0
F
/(2
X N)
CLKP1
19
1
F
/(2
X N)
CLKP1
: Peripheral clock (CLKP1) frequency
: Subclock (CLKSC) or RC-Clock (CLKRC) frequency
CHAPTER 26 LCD CONTROLLER/DRIVER
Display mode
When sub clock CLKSC or RC-
Clock CLKRC is selected
8
F
/(2
X N)
CL
9
F
/(2
X N)
CL
10
F
/(2
X N)
CL
11
F
/(2
X N)
CL
675
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