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CHAPTER 31 MEMORY PATCH FUNCTION
■ Patch function control/status register (PFCS0 to PFCS3)
Figure 31.2-3 Patch function control/status register (PFCS0/1/2/3)
Address:
PFCS0
0003B0
H
Access:
Address:
0003B2
PFCS1
H
Access:
Address:
PFCS2
0003B4
H
Access:
Address:
PFCS3
0003B6
H
Access:
R/W : Readable and writable
R/W0 : Readable and writable, but only clear possible
The patch function control/status register (PFCSx) controls the operation of the memory patch function and
reflects the status of each MPF channel. Each register word PFCSx belongs to a group of two channels.
For a detailed description of the control and status bits refer to Table 31.2-1. The functions controlled by
each bit in the PFCS1 to PFCS3 registers are identical to PFCS0, only the channel index of the PFA and PFD
registers have to be incremented by 2/4/6 accordingly.
Table 31.2-1 Function of each bit of the PFCS0 (MPF channel 0 and 1)
Name
bit 15
bit 14
820
15
14
13
12
11
10
READWRITE BYTE WORDCODE
DATA CPU DMA
R/W R/W R/W R/W R/W
R/W R/W R/W
15
14
13
12
11
10
READWRITE BYTE WORDCODE
DATA CPU DMA
R/W R/W R/W R/W R/W
R/W R/W R/W
15
14
13
12
11
10
READWRITE BYTE WORDCODE
DATA CPU DMA
R/W R/W R/W R/W R/W
R/W R/W R/W
15
14
13
12
11
10
READWRITE BYTE WORDCODE
DATA CPU DMA
R/W R/W R/W R/W R/W
R/W R/W R/W
READ
This bit controls, if read accesses are considered for the address match detection.
This includes the read part of read-modify-write.
• Writing '0' - Read accesses do not match.
• Writing '1' - Read accesses match.
• The bit can be read and written.
The READ bit is cleared after reset.
WRITE
This bit controls, if write accesses are considered for the address match detection.
• Writing '0' - Write accesses do not match.
• Writing '1' - Write accesses match.
• The bit can be read and written.
The WRITE bit is cleared after reset.
MB96300 Super Series Hardware Manual
9
8
7
6
5
4
3
AM
AR
PE1 PE0
IE1
R/W R/W R/W R/W R/W
9
8
7
6
5
4
3
AM
AR
PE1 PE0
IE1
R/W R/W R/W R/W R/W
9
8
7
6
5
4
3
AM
AR
PE1 PE0
IE1
R/W R/W R/W R/W R/W
9
8
7
6
5
4
3
AM
AR
PE1 PE0
IE1
R/W R/W R/W R/W R/W
Function
2
1
0
Initial value
0000
IE0
I1
I0
H
R/W R/W0 R/W0
Initial value
2
1
0
0000
IE0
I1
I0
H
R/W R/W0 R/W0
2
1
0
Initial value
0000
IE0
I1
I0
H
R/W R/W0 R/W0
Initial value
2
1
0
0000
IE0
I1
I0
H
R/W R/W0 R/W0
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