Table of Contents
Advertisement
MB96300 Super Series Hardware Manual
the Main clock timer is activated 700 RC clock cycles after a RST falling edge or 700 RC clock cycles after
clearing a power-on or low voltage event. Thus the Main oscillation stabilization wait time takes place even
if RST is still asserted.
●
PCM bit
The PLL is always disabled and the PLL clock ready monitor bit PCM cleared by reset. The PLL must be
enabled by software after User program start.
■ Start of program execution after Power or External reset
The RC clock timer starts counting after deactivation of PRST and ERST. After 64 RC clock cycles
(approximately 30µs at 2MHz nominal RC clock frequency), the RC clock ready monitor bit RCM will be
set and the internal reset signal for the CPU will be released. After reset release, the CPU is always in RC
clock mode with the RC clock frequency set to nominal 2MHz and starts executing the Boot ROM program.
The low Voltage Detector level (LVL bits of CILCR register) is initialized to the lowest possible value. If a
higher detection value should be needed, the register value can be changed accordingly.
See also section 8.2 "Reset, System clock and Stabilization Wait Times" for more details.
■ Transition to Main clock mode
A transition to Main clock mode is done by writing to the System clock select bits of the CKSR register.
The transition however is delayed until the Main clock is stabilized which is indicated by the Main Clock
ready Monitor bit MCM (set to "1").
The stabilization time of the Main oscillator is defined by the CKSSR: MCST[2:0] bits as described in
section 8.2 "Reset, System clock and Stabilization Wait Times".
Note: Use of the Fast Clock Input feature, which is optional on some devices, requires setting the FCI bit of
the CILCR register to 1 before switching to main clock mode. Please refer to the Datasheet for the input
characteristics of the oscillator pin.
■ Transition to PLL clock mode
The PLL must be configured and enabled by software. The PLL stabilization wait time takes place after PLL
activation and after stabilization of the Main clock (MCM="1").
A transition to PLL clock mode is possible when the PLL Clock ready Monitor bit PCM is set.
It is possible to directly switch from RC clock mode to PLL clock mode or via Main clock mode.
■ Transition to Sub clock mode
The Sub oscillator is enabled by each reset and the Sub clock stabilization time starts after PRST and ERST
are released.
The stabilization time of the Sub oscillator is determined by the CKSSR: SCST[1:0] bits which define when
the Sub Clock ready Monitor bit SCM will be set. A transition to Sub clock mode is delayed until SCM is set
to "1".
CHAPTER 8 RESETS AND STARTUP
199
Advertisement
Table of Contents
