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FUJITSU SEMICONDUCTOR
FME-MB96300 rev 14,
2007-12-18
CONTROLLER MANUAL
2
F
MC-16FX
16-BIT MICROCONTROLLER
MB96300 Super series
HARDWARE MANUAL

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   Summary of Contents for Fujitsu MB96300 series

  • Page 1

    FUJITSU SEMICONDUCTOR FME-MB96300 rev 14, 2007-12-18 CONTROLLER MANUAL MC-16FX 16-BIT MICROCONTROLLER MB96300 Super series HARDWARE MANUAL...

  • Page 3

    MC-16FX 16-BIT MICROCONTROLLER MB96300 Super series HARDWARE MANUAL FUJITSU LIMITED...

  • Page 5

    MB96300 Super Series Hardware Manual PREFACE ■ Objectives and intended reader Thank you very much for your continued patronage of Fujitsu semiconductor products. The MB96300 Super series has been developed as a general-purpose version of the F MC-16FX series, which is an original 16-bit single-chip microcontroller compatible with the Application Specific IC (ASIC).

  • Page 6

    MB96300 Super Series Hardware Manual CHAPTER 9 "STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT" This chapter explains the functions and operations of the standby mode control circuit and the control of the internal voltage regulator. The regulator control can be used to optimize power consumption, especially in standby modes.

  • Page 7

    MB96300 Super Series Hardware Manual CHAPTER 25 "CLOCK CALIBRATION UNIT" This chapter explains the functions and operation of the Clock Calibration Unit CHAPTER 26 "LCD CONTROLLER/DRIVER" This chapter describes the functions and operations of the LCD Controller/Driver. CHAPTER 27 "STEPPER MOTOR CONTROLLER" This chapter explains the functions and operations of the stepper motor controller.

  • Page 8

    (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.

  • Page 9: Table Of Contents

    MB96300 Super Series Hardware Manual CONTENTS OVERVIEW 7 Features 8 Super series lineup 10 Block Diagram of MB96V300 12 General note on using this document 16 16-bit I/O-Timer Configuration 19 Input Capture Unit source select for LIN-USART 23 Peripheral resource pin relocation 30 CPU 47 Outline of the CPU 48 Hardware Structure 50...

  • Page 10: Table Of Contents

    MB96300 Super Series Hardware Manual Clock Control Registers 148 Clock Modes 169 Configuration of the PLL 172 Oscillation Stabilization Wait Time 175 Connection of an Oscillator or an External Clock to the Microcontroller 177 CLOCK MODULATOR 179 Overview 180 Register Description 181 Application Note 188 RESETS AND STARTUP 191 Resets 192...

  • Page 11: Table Of Contents

    MB96300 Super Series Hardware Manual I/O PORTS 349 I/O Ports 350 I/O Port Registers 351 Register usage 362 16-BIT I/O TIMER 363 Outline of 16-bit I/O Timer 364 16-Bit I/O Timer Registers 366 16-bit Free-Running Timer 368 Output Compare Unit 375 Input Capture Unit 388 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) 395 Outline of 16-Bit Reload Timer (with Event Count Function) 396...

  • Page 12: Table Of Contents

    MB96300 Super Series Hardware Manual Configuration of USART 469 USART Pins 474 USART Registers 475 USART Interrupts 496 USART Baud Rates 503 Operation of USART 511 Notes on Using USART 535 400 kHz I2C INTERFACE 541 I2C Interface Overview 542 I2C Interface Registers 544 I2C Interface Operation 567 Programming Flow Charts 570...

  • Page 13: Table Of Contents

    MB96300 Super Series Hardware Manual Cautions 688 STEPPER MOTOR CONTROLLER 691 Outline of Stepper Motor Controller 692 Stepper Motor Controller Registers 693 PWM Control register (PWCn) 695 PWM Extended Control register (PWECn) 697 PWM1 and PWM2 Compare Registers (PWC1n, PWC2n) 698 PWM1 and PWM2 Selection registers (PWS1n, PWS2n) 701 Operation of Stepper Motor Controller 703 Notes on Using Stepper Motor Controller 706...

  • Page 14: Table Of Contents

    MB96300 Super Series Hardware Manual Notes on using Flash Memory 881 Flash memory programming example 882 MASK-ROM MEMORY INTERFACE 889 Overview 890 ROM interface registers 891 Read buffers 896 ROM/FLASH SECURITY 897 Overview of the ROM/Flash Security 898 Usage of the ROM/Flash Security 899 EXAMPLES OF SERIAL PROGRAMMING CONNECTION 903 Basic Configuration of Serial Programming Connection 904 Example of connecting a PC for programming the Flash Microcontroller 907...

  • Page 15: Overview

    CHAPTER 1 OVERVIEW The MB96300 Super series is a family member of the MC-16FX micro controllers. It consist of many different series of microcontrollers, which are targetting different applications. Programming between all members of the Super series is common. 1.1 "Features" 1.2 "Super series lineup"...

  • Page 16: Features

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual Features The feature set of F MC-16FX family’s MB96300 Super series makes it especially well suited for automotive applications.

  • Page 17

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Features • 16-bit core CPU, 64 MHz internal, 15.6 ns instruction cycle time • 0.18µm CMOS Process Technology • Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes;...

  • Page 18: Super Series Lineup

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual Super series lineup Table 1.2-1 "MB96300 super series lineup" provides an overview of the MB96300 Super series.

  • Page 19

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Super series lineup The F MC-16FX MB96300 Super series covers the F MC-16FX series as shown in table 1.2-1. Table 1.2-1 MB96300 super series lineup Series Flash Mask ROM Packages Products Products MB96320 MB96F32x...

  • Page 20: Block Diagram Of Mb96v300

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual Block Diagram of MB96V300 Figure 1.3-1 shows the block diagram of MB96V300.

  • Page 21

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Block Diagram of MB96V300...

  • Page 22

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual Figure 1.3-1 Block Diagram of MB96V300 AD00 ... AD15 CKOT0, CKOT1 A00 ... A23 CKOTX0, CKOTX1 WRLX, WRHX X0, X1 X0A, X1A RSTX HAKX MD0...MD2 LBX, UBX CS0 ... CS5 Emulation Memory Patch Clock &...

  • Page 23

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW Notes: USB is not available for MB96v300. Please refer to the datasheet of your device.

  • Page 24: General Note On Using This Document

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual General note on using this document This chapter contains some general notes about this document.

  • Page 25

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Device dependent resources The derivatives of a Microcontroller series may have different sets of resources (e.g. features, number of channels, interconnections). Details about an individual device can be found in the following documents: •...

  • Page 26

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Described resources All chapters about resources of the Microcontroller like USART, Reload timers, General purpose ports describe the function of only one channel of this resource. The behavior of all other resources of the same type is the same.

  • Page 27: Bit I/o-timer Configuration

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW 16-bit I/O-Timer Configuration The number of available Free Running timers, Input Capture Units and Output Compare Units differs between different devices. Multiple Input Capture Units and Output Compare Units are connected to one Free Running timer. This chapter describes the relation between these modules.

  • Page 28

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Connection between Input Capture Units and Free Running Timers Table 1.5-1 Connection between Input Capture Units and Free Running Timers Free Running Input Capture Unit Timer MB96V300 MB9632x MB9633x MB9634x MB9635x MB9636x MB9638x FRT0...

  • Page 29

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Connection between Output Compare Units and Free Running Timers Table 1.5-2 Connection between Output Compare Units and Free Running Timers Free Output compare unit Running Timer MB96V300 MB9632x MB9633x MB9634x MB9635x MB9636x MB9638x FRT0...

  • Page 30

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Relation between Timer clear function and OCU, Compare clear and Free running timer Table 1.5-3 Connection between OCU, Compare clear and Free running timer for timer clear Free running Timer is cleared at match with following Note timer compare register...

  • Page 31: Input Capture Unit Source Select For Lin-usart

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW Input Capture Unit source select for LIN-USART The input source for the Input Capture units can be selected between an external pin (INx) and the LIN-USART Sync Field output. This chapter describes how to select the Input capture input and which LIN-USART can be connected to which ICU.

  • Page 32

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Overview of connection between LIN-USART and ICU Table 1.6-1 Connection between LIN-USARTs and ICUs Free running ICU source LIN-USART Device timer for ICU select bit USART0 ICU0 FRT0 ICE01:ICUS0 MB96V300, MB96(F)32x, MB96(F)33x, MB96(F)34x, MB96(F)36x,...

  • Page 33

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Input Capture Unit source select The source selection for ICU is done in the Input capture edge registers ICExy. Figure 1.6-1 Input capture edge register ICE01 Initial value X X X 0 X 0 0 0 Address: ICUS1 ICUS0...

  • Page 34

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual Figure 1.6-2 Input capture edge register ICE45 Initial value X X X 0 X 0 0 0 Address: ICUS5 ICUS4 IEI5 IEI4 00004d R/W R/W R/W bit8 IEI4 Input capture valid edge indication bit for ICU4 falling edge detected rising edge detected bit9...

  • Page 35

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW Figure 1.6-3 Input capture edge register ICE67 Initial value X X X 0 X 0 0 0 Address: ICUS7 ICUS6 IEI7 IEI6 000053 R/W R/W R/W bit8 IEI6 Input capture valid edge indication bit for ICU6 falling edge detected rising edge detected bit9...

  • Page 36

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual Figure 1.6-4 Input capture edge register ICE89 Initial value X X X 0 X 0 0 0 Address: ICUS9 ICUS8 IEI9 IEI8 000515 R/W R/W R/W bit8 IEI8 Input capture valid edge indication bit for ICU8 falling edge detected rising edge detected bit9...

  • Page 37

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW Figure 1.6-5 Input capture edge register ICE1011 Initial value X X X 0 X 0 0 0 Address: ICUS11 ICUS10 IE11 IEI10 00051b R/W R/W R/W bit8 IEI10 Input capture valid edge indication bit for ICU10 falling edge detected rising edge detected bit9...

  • Page 38: Peripheral Resource Pin Relocation

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual Peripheral resource pin relocation The input or output pin of some resources can be relocated. The location of these resource pins is defined by the peripheral resource pin relocation registers PRRR[9:0].

  • Page 39

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Overview of the peripheral resource relocation register Table 1.7-1 Peripheral resource pin relocation register (PRRR0 to PRRR13) Address Name BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Description Peripheral resource 0004d6 PRRR0 INT7_R INT6_R...

  • Page 40

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Peripheral resource relocation register 0 (PRRR0) Figure 1.7-1 Peripheral resource relocation register 0 (PRRR0) Initial value 0 0 0 0 0 0 0 0 Address: INT7_R INT6_R INT5_R INT4_R INT3_R INT2_R INT1_R INT0_R 0004d6 R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 41

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Peripheral resource relocation register 1 (PRRR1) Figure 1.7-2 Peripheral resource relocation register 1 (PRRR1) Initial value 0 0 0 0 0 0 0 0 Address: INT15_R INT14_R INT13_R INT12_R INT11_R INT_10R INT9_R INT8_R 0004d7 R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 42

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Peripheral resource relocation register 2 (PRRR2) Figure 1.7-3 Peripheral resource relocation register 2 (PRRR2) Initial value 0 0 0 0 0 0 0 0 Address: PPG7_R PPG6_R PPG5_R PPG4_R PPG3_R PPG2_R PPG1_R PPG0_R 0004d8 R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 43

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Peripheral resource relocation register 3 (PRRR3) Figure 1.7-4 Peripheral resource relocation register 3 (PRRR3) Initial value 0 0 0 0 0 0 0 0 Address: TOT3_R TIN3_R TOT2_R TIN2_R TOT1_R TIN1_R TOT0_R TIN0_R 0004d9 R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 44

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Peripheral resource relocation register 4 (PRRR4) Figure 1.7-5 Peripheral resource relocation register 4 (PRRR4) Initial value 0 0 0 0 0 0 0 0 Address: IN7_R IN6_R IN5_R IN4_R IN3_R IN2_R IN1_R IN0_R 0004da...

  • Page 45

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Peripheral resource relocation register 5 (PRRR5) Figure 1.7-6 Peripheral resource relocation register 5(PRRR5) Initial value 0 0 X X 0 0 0 0 Address: OUT7_R OUT6_R OUT3_R OUT2_R OUT1_R OUT0_R 0004db R/W R/W R/W R/W R/W bit8...

  • Page 46

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Peripheral resource relocation register 6 (PRRR6) Figure 1.7-7 Peripheral resource relocation register 6 (PRRR6) Initial value CKOT CKOT1_R SCK2_R SOT2_R SIN2_R FRCK0_R SGA0_R SGO0_R 0 0 0 0 0 0 0 0 Address: X1_R 0004dc...

  • Page 47

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Peripheral resource relocation register 7 (PRRR7) Figure 1.7-8 Peripheral resource relocation register 7 (PRRR7) Initial value 0 0 0 0 0 0 0 0 Address: TX2_R RX2_R INT5_R1 INT4_R1 INT3_R1 CS3_R NMI_R ADTG_R 0004dd R/W R/W R/W R/W R/W...

  • Page 48

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Peripheral resource relocation register 8 (PRRR8) Figure 1.7-9 Peripheral resource relocation register 8 (PRRR8) Initial value 0 0 0 0 0 0 0 0 Address: SOT9_R SIN9_R SCK8_R1 SOT8_R SIN8_R SCK7_R SOT7_R SIN7_R 0004de R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 49

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Peripheral resource relocation register 9 (PRRR9) Figure 1.7-10 Peripheral resource relocation register 9 (PRRR9) Initial value X X 0 0 0 0 0 0 Address: CKOT0_ROUT10_RFRCK2_R SGA1_R SGO1_R SCK9_R 0004dd R/W R/W R/W R/W R/W R/W R/W R/W bit0 SCK9_R...

  • Page 50

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Peripheral ressource relocation register 10 (PRRR10) Figure 1.7-11 Peripheral resource relocation register 10 (PRRR10) Initial value 0 0 0 0 0 0 0 0 Address: TTG11_RTTG10_R TTG9_R TTG8_R PPG11_R PPG10_R PPG9_R PPG8_R 000660 R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 51

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Peripheral ressource relocation register 11 (PRRR11) Figure 1.7-12 Peripheral resource relocation register 11 (PRRR11) Initial value 0 0 0 0 0 0 0 0 Address: TTG19_R TTG18_R TTG17_R TTG16_R PPG19_R PPG18_R PPG17_R PPG16_R 000661 R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 52

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual ■ Peripheral ressource relocation register 12 (PRRR12) Figure 1.7-13 Peripheral resource relocation register 12 (PRRR12) Initial value 0 0 0 0 0 0 0 0 Address: CS5_R CS4_R CS2_R CS1_R CS0_R 000662 R/W R/W R/W R/W R/W R/W R/W R/W bit0...

  • Page 53

    MB96300 Super Series Hardware Manual CHAPTER 1 OVERVIEW ■ Peripheral ressource relocation register 13 (PRRR13) Figure 1.7-14 Peripheral resource relocation register 13 (PRRR13) Initial value 0 0 0 0 0 0 0 0 Address: 000663 R/W R/W R/W R/W R/W R/W R/W R/W bit0 - bit7 reserved bit...

  • Page 54

    CHAPTER 1 OVERVIEW MB96300 Super Series Hardware Manual...

  • Page 55

    CHAPTER 2 This chapter explains the CPU. 2.1 "Outline of the CPU" 2.2 "Hardware Structure" 2.3 "Memory Space" 2.4 "Special Registers" 2.5 "General-Purpose Registers" 2.6 "Prefix Codes"...

  • Page 56: Outline Of The Cpu

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual Outline of the CPU The F MC-16FX CPU core is a 16-bit CPU designed for applications that require high- speed real-time processing, such as home-use or vehicle-mounted electronic appliances. The F MC-16FX instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing.

  • Page 57

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU • Instruction set symmetry • Shift instructions...

  • Page 58: Hardware Structure

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual Hardware Structure This section explains the hardware structure of the CPU and the 16FX core. ■ Hardware Structure of the CPU ● CPU Block Diagram Figure 2.2-1 CPU block diagram Instruction Fetch stage F2MC−16FX CPU Queue Decode Address...

  • Page 59

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU • Write back (WB): Writes the operation result to a register or memory location. Figure 2.2-2 Instruction Pipeline Instruction 1 Instruction 2 Instruction 3 Instruction 4 Instruction 5 Instruction 6 Instructions are not executed out of order. Therefore, if instruction A enters the pipeline ahead of instruction B, instruction A always reaches write back stage before instruction B.

  • Page 60

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual Figure 2.2-3 MCU Device based on the 16FX Core User Ports F2MC−16FX Boot ROM Interrupt Controller (program area) Controller (data area) Timer Serial Clock and Peripheral Mode Control Bus Bridge Peripheral Bus 1 External Bus Peripheral Interface...

  • Page 61

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU ● External Bus Interface The external bus interface is an optional component. Its availability depends on the configuration of the specific device. ● Boot ROM After device initialization by reset, the program counter points to the boot ROM. The CPU starts the execution of the boot ROM program.

  • Page 62: Memory Space

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual Memory Space An F MC-16FX CPU has a 16-Mbyte memory space. 2.3.1 "Memory Areas" 2.3.2 "Linear Addressing Method" 2.3.3 "Bank Addressing Method" 2.3.4 "Multi-byte Data in Memory Space"...

  • Page 63

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.3.1 Memory Areas All I/O addresses, programs and data are located in the 16-megabyte memory space of the F MC-16FX CPU. The CPU is able to access each resource through an address indicated by the 24-bit address bus.

  • Page 64

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual ■ I/O area The address range of the I/O area is from 00:0000 to 00:00FF . This address range can be used for direct I/ O addressing by specifying the 8 bit address as operand together with the instruction. If an instruction is using the direct I/O addressing method, the register is accessed regardless of the values specified by the direct page register (DPR) or the data bank register (DTB).

  • Page 65

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU ● Mirror area in bank 00 (address: 00:8000 to 00:FFFF This area is used to access the top-most section of 32 kByte ROM by default. The ROM mirror function is variable in size. There are up to 4 segments of 8 kByte each selectable as ROM mirror. The ROM bank to be accessed via bank 00 can be selected in the ROMM register.

  • Page 66

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual 2.3.2 Linear Addressing Method At linear addressing an entire 24-bit address is specified by an instruction. There are two types of linear addressing: • 24-bit operand specification: Directly specifies a 24-bit address using operands. •...

  • Page 67

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.3.3 Bank Addressing Method In the bank addressing method the eight high-order bits of an address are specified by an appropriate bank register, and the remaining 16 low-order bits are specified by an instruction.

  • Page 68

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual instruction. This enables access to the bank space corresponding to the specified prefix code. Table 2.3-2 Bank selection prefixes Bank selection prefix Selected Space Program space Data space Additional data space Either the system or the user stack space is used, according to the stack flag status upon selection.

  • Page 69

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU bank 00 (000000 to 00FFFF ), and the PC space is allocated in the bank specified by the reset vector. Table 2.3-3 Initialization of bank registers Bank register Initialization by reset Initialization by Boot ROM External vector mode Internal vector mode Byte read from...

  • Page 70

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual 2.3.4 Multi-byte Data in Memory Space Data is written to memory from the low-order address on. Therefore, for a 32-bit data item, the low-order 16 bits are transferred before the high-order 16 bits. If a reset signal is input immediately after the low-order bits are written, the high-order bits might not be written.

  • Page 71: Special Registers

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU Special Registers The F MC-16FX CPU registers are classified into two types: special registers and general-purpose registers. This section explains the special registers of the F MC-16FX CPU. The special registers are dedicated internal hardware of the CPU, and they have specific use defined by the CPU architecture.

  • Page 72

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual ■ Special registers The F MC-16FX CPU has the following special registers: • Accumulator (A=AH:AL): Two 16-bit accumulators (can be used as a single 32-bit accumulator) • User stack pointer (USP): 16-bit user stack pointer •...

  • Page 73

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.4.1 Accumulator (A) The accumulator (A) register consists of two 16-bit arithmetic operation registers (AH and AL), and is used as a temporary storage for operation results and transfer data. ■ Accumulator (A) The A register consists of two 16-bit arithmetic operation registers (AH and AL).

  • Page 74

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual Figure 2.4-3 Example of AL-AH transfer by means of data preservation MOVW A, @RW1+6 Previous content XXXX 1234 A61540 of the A register A6153E Latest content of the A register 1234 2B52...

  • Page 75

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.4.2 User Stack Pointer (USP) and System Stack Pointer (SSP) USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data when a push/pop instruction or subroutine is executed. ■...

  • Page 76

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual drawback in stack performance.

  • Page 77

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.4.3 Processor Status (PS) The PS register consists of the bits controlling the CPU Operation and indicating the CPU status. ■ Processor status (PS) As shown in Figure 2.4-5“Processor status (PS) structure”, the high-order byte of the PS register consists of a register bank pointer (RP) and an interrupt level mask register (ILM).

  • Page 78

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual ● S: Stack flag: When the S flag is 0, USP is enabled as the stack pointer. When the S flag is 1, SSP is enabled as the stack pointer. The S flag is set by an interrupt reception or a reset. ●...

  • Page 79

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU ■ Interrupt level mask register (ILM) The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt request is accepted only when the priority of the interrupt is higher than that indicated by the ILM register and the P flag.

  • Page 80

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual Table 2.4-1 Levels indicated by the P flag and interrupt level mask (ILM) register Level P flag ILM value Acceptable interrupt level none Interrupts disabled Level < P1 Interrupts disabled Level < P2 Interrupts disabled Level <...

  • Page 81

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.4.4 Program Counter (PC) The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address of an instruction code to be executed by the CPU. ■ Program counter (PC) The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address of an instruction code to be executed by the CPU.

  • Page 82

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual 2.4.5 Direct Page Register (DPR) The direct page register (DPR) specifies bits 8 to 15 (addr 8 to addr 15) of the operand address for direct addressing instructions. ■ Direct page register (DPR) DPR specifies bits 8 to 15 of the instruction operands in direct addressing mode as shown in Figure 2.4- 10"Generating a physical address in direct addressing mode".

  • Page 83

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.4.6 Bank register (PCB, DTB, ADB, USB, SSB) Each bank register indicates a memory bank where a program space, data space, user stack space or additional data space is allocated ■ Bank Register All bank registers are one byte long.

  • Page 84: General-purpose Registers

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual General-Purpose Registers The F MC-16FX CPU registers are classified into two types: special registers and general-purpose registers. This section explains the general-purpose registers (GPRs) of the F2MC-16FX CPU. GPRs can be accessed without addressing, similar to the special registers. The register operations are defined by specific instructions.

  • Page 85

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.5.1 Register Bank A register bank consists of eight words. The register bank can be used as general- purpose registers for arithmetic operations. ■ Register bank A register bank consists of eight words. The register bank can be used as the following general-purpose registers for arithmetic operations: •...

  • Page 86

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual In the same manner as for an ordinary RAM area, the register bank values are not initialized by a reset. The status before a reset is maintained. When the power is turned on, the register bank will have an undefined value.

  • Page 87

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.5.2 Addressing General-Purpose Registers The general-purpose registers of the F MC-16FX use the register bank pointer (RP) to specify the currently used register bank. The register banks can be addressed between 00:0180 and 00:037F in the memory space.

  • Page 88: Prefix Codes

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual Prefix Codes Placing a prefix code before an instruction partially changes the operation of that instruction. There are three types of prefix codes: • Bank selection prefix • Common register bank prefix •...

  • Page 89

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.6.1 Bank Selection Prefix Placing a bank selection prefix before an instruction enables that instruction to access any specified memory space, regardless of the addressing method being used. ■ Bank select prefix The memory space used for accessing data is determined for each addressing mode.

  • Page 90

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual ● Branch instructions RETI The system stack bank (SSB) is used, regardless of any bank selection prefix is specified. ● String operation instructions FILS FILSW SCEQ SCWEQ MOVS MOVSW The bank register specified by the operand is used, regardless of any bank selection prefix is specified. ●...

  • Page 91

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.6.2 Common Register Bank Prefix (CMR) The common register bank prefix (CMR) can be placed before an instruction that accesses a register bank. Then the target register of that instruction is changed to the common register bank.

  • Page 92

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual The specified prefix affects the next instruction.

  • Page 93

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.6.3 Flag Change Inhibit Prefix (NCC) Flag changes associated with the execution of an instruction can be inhibited by placing a flag change inhibit prefix code (NCC) before that instruction. ■ Flag change inhibit prefix code (NCC) To disable flag changes, use the flag change inhibit prefix code (NCC).

  • Page 94

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual CCR changes according to the instruction specifications regardless of the prefix.

  • Page 95

    MB96300 Super Series Hardware Manual CHAPTER 2 CPU 2.6.4 Prefix Code Restrictions This section lists the instructions, which reject interrupt requests during execution. If a prefix code is placed before such an instruction, the setting of the prefix code remains effective until the first instruction is executed after this interrupt rejecting instruction.

  • Page 96

    CHAPTER 2 CPU MB96300 Super Series Hardware Manual Figure 2.6-2 Interrupt rejecting instructions and prefix codes Interrupt rejecting instruction • • • • ADD A,01 H MOV A, FF H MOV ILM,#imm8 CCR:XXX10XX CCR:XXX10XX CCR does not change with NCC. ■...

  • Page 97: Interrupts

    CHAPTER 3 INTERRUPTS This chapter explains the interrupt functions and operations. 3.1 "Outline of Interrupts" 3.2 "Interrupt Vector" 3.3 "Interrupt Control Registers (ICR)" 3.4 "Non Maskable Interrupt (NMI)" 3.5 "Interrupt Flow" 3.6 "Hardware Interrupts" 3.7 "Software Interrupts" 3.8 "Multiple interrupts" 3.9 "Exceptions"...

  • Page 98: Outline Of Interrupts

    CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual Outline of Interrupts The F MC-16FX has interrupt functions that terminate the currently executed program and transfer control to another specified program when a specific event occurs. There are four types of interrupt functions: •...

  • Page 99

    MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS • NMI • HW-INT9 (embedded debug support) • DSU break factors (only available on the EVA device) Exception processing is basically the same as interrupt processing. When an exception is detected during instruction execution, exception processing is performed.

  • Page 100: Interrupt Vector

    CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual Interrupt Vector Hardware and software interrupts use the same vector table. The execution of interrupt service routines can be triggered by asserting the specific IRQ line or by executing the INT instruction and specifying the number of the interrupt vector. Interrupt vectors are allocated between addresses as shown in Table 3.2-2 "Interrupt vector table".

  • Page 101

    MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS ● Interrupt Vector Table The interrupt vector table referenced during interrupt processing is assigned to addresses 256*TBR to 256*TBR+3FF in memory. The reset defaults are from FFFC00 to FFFFFF for the location of the vector table.

  • Page 102

    CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual Table 3.2-2 Interrupt vector table Interrupt / Vector number Vector address Index of level Hardware IRQ / Interrupt cause register in ICR INT 17 TB+3B8 IL17 Device specific peripheral. INT 18 TB+3B4 IL18 Device specific peripheral.

  • Page 103: Interrupt Control Registers (icr)

    MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS Interrupt Control Registers (ICR) For each peripheral resource that has an interrupt function, there is an interrupt control register (ICR). The interrupt control register sets the interrupt level (IL) for the peripheral resource it is assigned to.

  • Page 104

    CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual indexed access: - Use word access to write information to ICR:IX and ICR:IL simultaneously. - At read access, set the index ICR:IX and read the whole ICR register using word access. Check the ICR:IX value to match the intended index to be read for validation of the correct ICR:IL entry.

  • Page 105: Non Maskable Interrupt (nmi)

    MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS Non Maskable Interrupt (NMI) The F2MC-16FX CPU has a non maskable interrupt. The feature of the external NMI pin can be enabled, it’s level can be defined and a flag to quit the NMI request is provided. ■...

  • Page 106

    CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual processing, if an active signal level is detected at the NMI pin (defined by the LEV bit). If EN is set to ’1’, both the LEV and EN bits are locked for writing. Neither the signal level can be changed nor the NMI can be disabled after the NMI feature was enabled once.

  • Page 107: Interrupt Flow

    MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS Interrupt Flow Figure 3.5-2 "Interrupt flow" shows the interrupt flow. ■ Interrupt flow The interrupt processing flow is entered at occurrence of hardware interrupts, software interrupts or exceptions. For a detailed interrupt flow chart see Figure 3.5-2 "Interrupt flow". The CPU special registers are saved on the stack before the interrupt is processed (see Figure 3.5-1 "Register saving during interrupt processing").

  • Page 108

    CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual Figure 3.5-2 Interrupt flow I, ILM: Interrupt flag and interrupt level mask in CCR/PS of CPU START IF, IE: Internal resource interrupt request flag and enable DER: DMA enable register of the related DMA channel Level configuration of the IRQ channel by ICR/ILR System stack flag in the CCR/PS DISEL: DMA intserrupt select register...

  • Page 109: Hardware Interrupts

    MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS Hardware Interrupts In response to an interrupt request signal from an internal resource, the CPU pauses current program execution and transfers control to the interrupt processing program defined by the user. ■ Hardware interrupts A hardware interrupt occurs when the relevant conditions are satisfied as a result of two operations: •...

  • Page 110

    CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual interrupts, the I flag has to be set and ILM has to be larger than IL. - During interrupt processing, the CPU saves 12 bytes to the memory area indicated by SSB and SSP. Thus the system stack pointer has to be initialized before using interrupts.

  • Page 111

    MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS - If the final transfer count is reached, the DMA completion interrupt is processed by the interrupt controller. 4. The interrupt controller receives the interrupt request. 5. The interrupt controller determines the priority levels of simultaneously requested interrupts. 6.

  • Page 112: Software Interrupts

    CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual Software Interrupts In response to execution of a special instruction, control is transferred from the program currently executed by the CPU to the interrupt processing program defined by the user. This is called the software interrupt function. A software interrupt occurs always when the software interrupt instruction is executed.

  • Page 113

    MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS Figure 3.7-1 Occurrence and release of software interrupt (2b) Register File Stack clear (2c) (2a) Execution Pipeline INT (1) Instruction Queue F2MC−16FX CPU Processing of the RETI Interrupt Service Instruction (4) Routine (3) Instruction (1) 1.

  • Page 114: Multiple Interrupts

    CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual Multiple interrupts The F MC-16FX CPU supports multiple interrupts (simultaneous occurring interrupts and nested interrupt processing). ■ Multiple hardware interrupts If an hardware interrupt of a higher priority (lower level value) occurs while another interrupt is being processed, control is transferred to the higher priority interrupt after the currently executing instruction is completed.

  • Page 115

    MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS ■ Interrupt acceptance priority Following table lists all interrupts with conditions for their acceptance.

  • Page 116

    CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual Table 3.8-1 Control of interrupt acceptance priority Event INT# Type Level Acceptance condition Action, if accepted Instruction Break Current instruction execution is Save CPU P = 0 (VEIB) finished, status to ILM = 2 system reserved ILM>2 || P == 1 system stack...

  • Page 117

    MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS System stack flag Privileged mode flag (bit 7 of CCR, PS) Following table defines the naming of the interrupt levels, its corresponding P flag and ILM values. It also lists the interrupt cause, which can request the interrupt level. Table 3.8-2 Interrupt levels Name Category...

  • Page 118: Exceptions

    CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual Exceptions The F MC-16FX performs exception processing at occurrence of various software and hardware events. ■ Software exceptions (op-code) Software exceptions are always accepted. Same as software interrupts, software exceptions disable any hardware interrupt acceptance.

  • Page 119

    MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS ● INTE (System reserved, only available with DSU) INTE is used to insert a software break point for the debug system, using the in circuit emulator (ICE). At insertion of a software instruction break, the first byte of the original instruction is replaced by INTE. This instruction branches to the interrupt processing routine indicated by a fixed vector defined by the DSU.

  • Page 120

    CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual (SSP)<-(SSP)-2, ((SSP))<-(PC) (SSP)<-(SSP)-2, ((SSP))<-(PS) (S)<-1, (P)<-0, (ILM)<-6 (PCB)<-Vector #9 address (upper byte) (PC)<-Vector #9 address (lower word) ● NMI provides external hardware exception handling. The privileged mode flag (P flag) is cleared and ILM is set to 4 (enters level P4). This disables all hardware interrupts from peripherals and the HW-INT9.

  • Page 121

    MB96300 Super Series Hardware Manual CHAPTER 3 INTERRUPTS...

  • Page 122

    CHAPTER 3 INTERRUPTS MB96300 Super Series Hardware Manual...

  • Page 123

    CHAPTER 4 This chapter explains the DMA functions and operations. 4.1 "Overview" 4.2 "DMA Registers" 4.3 "DMA Descriptor" 4.4 "DMA Controller Operation" 4.5 "Examples of DMA transfers"...

  • Page 124

    CHAPTER 4 DMA MB96300 Super Series Hardware Manual Overview DMA enables automatic data transfer between memory and memory/peripheral resource registers or vice versa without interaction of the CPU. DMA replaces 16LX family’s EI while offering the extended functionality at higher performance. This section describes the DMA functions.

  • Page 125

    MB96300 Super Series Hardware Manual CHAPTER 4 DMA • Automatic data transfer between peripheral resources (I/O) and memory • CPU bus allocation during DMA transfer • Up to 16 DMA transfer channels with fixed priority scheme (the smaller the DMA channel number, the higher the priority of the request).

  • Page 126

    CHAPTER 4 DMA MB96300 Super Series Hardware Manual - I and ILM are used to compare the requested and current interrupt levels and to identify the interrupt enable status. - If the interrupt level is accepted, the CPU handles the interrupt request.

  • Page 127: Dma Registers

    MB96300 Super Series Hardware Manual CHAPTER 4 DMA DMA Registers The DMA controller has three registers (DER, DSR, DSSR, each with one bit per DMA channel) and one register to select the interrupt (DISEL, one byte for each DMA channel). The DMA descriptor is used to set-up the DMA transfer.

  • Page 128

    CHAPTER 4 DMA MB96300 Super Series Hardware Manual Write operations to not available bits/registers have no effect.

  • Page 129

    MB96300 Super Series Hardware Manual CHAPTER 4 DMA 4.2.1 DMA Interrupt Request Select Register (DISEL) Each DMA channel has one Interrupt Request Select Register (DISEL0 ... DISEL15). This register defines which IRQ number is used to trigger the DMA transfer on this channel. ■...

  • Page 130

    CHAPTER 4 DMA MB96300 Super Series Hardware Manual 4.2.2 DMA Status Register (DSR) This section describes the DMA Status Register (DSR). ■ DMA Status Register (DSR) Figure 4.2-3 DMA Status Register (DSR) configuration Bit No. Address: DTE15 DTE14 DTE13 DTE12 DTE11 DTE10 DTE9 DTE8 DTE7 DTE6 DTE5 DTE4 DTE3 DTE2 DTE1 DTE0 DSRH, DSRL 0x391, 0x390...

  • Page 131

    MB96300 Super Series Hardware Manual CHAPTER 4 DMA 4.2.3 DMA Stop Status Register (DSSR) This section describes the DMA Stop Status Register (DSSR) ■ DMA Stop Status Register (DSSR) Figure 4.2-4 DMA Stop Status Register (DSSR) configuration Bit No. Address: STP15 STP14 STP13 STP12 STP11 STP10 STP9 STP8 STP7 STP6 STP5 STP4 STP3 STP2 STP1 STP0 DSSRH, DSSRL...

  • Page 132

    CHAPTER 4 DMA MB96300 Super Series Hardware Manual 4.2.4 DMA Enable Register (DER) This section describes the DMA Enable Register (DER). ■ DMA Enable Register (DER) Figure 4.2-5 DMA Enable Register (DER) configuration Bit No. Address: EN15 EN14 EN13 EN12 EN11 EN10 EN9 DERH, DERL 0x395, 0x394 Read/Write:...

  • Page 133: Dma Descriptor

    MB96300 Super Series Hardware Manual CHAPTER 4 DMA DMA Descriptor For each DMA channel the DMA descriptor consists of 8 bytes. It is used to set-up DMA transfer. ■ Configuration of DMA Descriptors Each DMA channel has its own DMA descriptor of 8 bytes. The DMA descriptors are located from addresses 000100 to 00017F .

  • Page 134

    CHAPTER 4 DMA MB96300 Super Series Hardware Manual Figure 4.3-1 Configuration of the DMA Descriptor Address: Access Initial value: 0x000107 + 8*ch Upper 8 bits of data counter (DCTH) (R/W) 0x000106 + 8*ch Lower 8 bits of data counter (DCTL) (R/W) 0x000105 + 8*ch Upper 8 bits of I/O register address pointer (IOAH)

  • Page 135

    MB96300 Super Series Hardware Manual CHAPTER 4 DMA 4.3.1 Data Count Register (DCT) This section describes the Data Count Register (DCT). ■ Data Count Register (DCT) The Data Count Register (DCT) is a 16-bit register to store the number of bytes to be transferred. After each data transfer, the Data Count Register is decremented by 1 at byte transfer or by 2 at word transfer.

  • Page 136

    CHAPTER 4 DMA MB96300 Super Series Hardware Manual 4.3.2 I/O Register Address Pointer (IOA) This section describes the I/O Register Address Pointer (IOA). ■ I/O Register Address Pointer (IOA) The I/O Register Address Pointer (IOA) is a 16-bit register and indicates the lower addresses (A15 to A0) of the I/O register.

  • Page 137

    MB96300 Super Series Hardware Manual CHAPTER 4 DMA 4.3.3 DMA Control Register (DMACS) This section describes the DMA Control Register (DMACS). ■ DMA Control Register (DMACS) The DMA Control Register (DMACS) is 8-bit long and is used: • to specify, if the Buffer Address Pointer should be incremented or decremented (BPD) •...

  • Page 138

    CHAPTER 4 DMA MB96300 Super Series Hardware Manual Figure 4.3-4 Configuration of DMACS Address: Bit No. 8*ch + 0x103 − − DMACS Read/Write: (−) (−) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial Value: readable and writable R/W: no access; read returns undefined value, write always 0 to this bit −: [bit 13] BPD: Buffer pointer decrement bit BPD bit...

  • Page 139

    MB96300 Super Series Hardware Manual CHAPTER 4 DMA [bit 9] DIR: Data transfer direction DIR bit Function Transfer from address specified by IOA to address specified by BAP (@IOA -> @BAP). Transfer from address specified by BAP to address specified by IOA (@BAP ->...

  • Page 140

    CHAPTER 4 DMA MB96300 Super Series Hardware Manual 4.3.4 Buffer Address Pointer (BAP) This section describes the Buffer Address Pointer (BAP). ■ Buffer Address Pointer (BAP) The Buffer Address Pointer (BAP) is a 24-bit register and is used to store addresses that will be used for DMA transfer.

  • Page 141: Dma Controller Operation

    MB96300 Super Series Hardware Manual CHAPTER 4 DMA DMA Controller Operation This section describes the DMA controller operation. ■ DMA Controller Operation Figure 4.4-1 "DMAC Operation" shows the DMA controller operation. Figure 4.4-1 DMAC Operation Peripheral function (I/O) I/O register I/O register (5a) DMA controller...

  • Page 142

    CHAPTER 4 DMA MB96300 Super Series Hardware Manual ■ Procedure for using DMAC Figure 4.4-2 Procedure for using DMAC Software processing Hardware processing Interrupt occurence Start DISELx == IRQ number Initialize the system stack Initialize the peripheral function DER:ENx == 1 and DSR:DTEx == 0 Set the interrupt control register STOP request and...

  • Page 143

    MB96300 Super Series Hardware Manual CHAPTER 4 DMA ■ Number of cycles for the data transfer The number of transfer cycles (bus cycles during DMA transfer) is the sum of all single transfers until DCT reaches 0. For reference of the number of cycles for a single DMA transfer, see Table 4.3-2, column "Transfer cycles".

  • Page 144: Examples Of Dma Transfers

    CHAPTER 4 DMA MB96300 Super Series Hardware Manual Examples of DMA transfers This sections describes some of the lesser ordinary DMA transfer types or circumstances. To simplify matters an even address somewhere in memory bank 00 is used as IOA in the following examples. These examples still hold if the addresses of IOA and BAP are exchanged, under the constraint that IOA must refer to memory bank 00 .

  • Page 145

    MB96300 Super Series Hardware Manual CHAPTER 4 DMA Figure 4.5-2 Transferring one word to/from an odd address 01CCAA 00BCDE ■ Word transfer with odd byte count When DCT is set to an odd number of bytes and word transfers are used, the last transfer moves only one byte.

  • Page 146

    CHAPTER 4 DMA MB96300 Super Series Hardware Manual Figure 4.5-4 Transfer of the last byte of a channel set to word transfer and BAP decrement High byte Low byte Transfer 0 Transfer 0 01CCAA 01CCA8 High byte Low byte Transfer n Transfer n 00BCDE ■...

  • Page 147: Delayed Interrupt

    CHAPTER 5 DELAYED INTERRUPT This chapter explains the functions and operations of the delayed interrupt. 5.1 "Outline of Delayed Interrupt Module" 5.2 "Delayed Interrupt Register" 5.3 "Delayed Interrupt Operation"...

  • Page 148: Outline Of Delayed Interrupt Module

    CHAPTER 5 DELAYED INTERRUPT MB96300 Super Series Hardware Manual Outline of Delayed Interrupt Module The Delayed Interrupt source module is used to generate interrupts for task switching. Using this module, interrupts to the F MC-16FX CPU can be requested and canceled by software.

  • Page 149: Delayed Interrupt Register

    MB96300 Super Series Hardware Manual CHAPTER 5 DELAYED INTERRUPT Delayed Interrupt Register DIRR controls request and cancellation of the Delayed Interrupt. Writing "1" to this register issues a delayed interrupt request, and writing "0" cancels the delayed interrupt request. ■ Delayed Interrupt Cause Issuance/Cancellation register (DIRR: Delayed Interrupt Request Register) Figure 5.2-1 Delayed Interrupt Cause/Cancel Register (DIRR) Address:...

  • Page 150: Delayed Interrupt Operation

    CHAPTER 5 DELAYED INTERRUPT MB96300 Super Series Hardware Manual Delayed Interrupt Operation When the CPU writes "1" to the relevant bit of DIRR by software, the request latch in the Delayed Interrupt source module is set and an interrupt request is issued to the interrupt controller.

  • Page 151: Clocks

    CHAPTER 6 CLOCKS This chapter describes the clocks used by F MC-16FX family micro controllers. 6.1 Clocks 6.2 Clock Control Registers 6.3 Clock Modes 6.4 Configuration of the PLL 6.5 Oscillation Stabilization Wait Time 6.6 Connection of an Oscillator or an External Clock to the Microcontroller...

  • Page 152

    CHAPTER 6 CLOCKS Clocks The F2MC-16FX MCU offers up to 4 different clock sources (RC clock, Main clock, PLL clock and Sub clock). Flexible clock dividers allow an independent setting of the Bus clock (for the internal bus with the CPU and memories) and for the Peripheral clocks frequencies.

  • Page 153

    CHAPTER 6 CLOCKS ■ Block Diagram The following block diagram shows the clock sources, the generation of the internal clocks and the source clock timers of the F2MC-16FX MCU. The different clocks are described below. See also CHAPTER 1 OVERVIEW for a block diagram showing which modules are connected to which clocks. Figure 6.1-1 Block diagram of the clock generation and source clocks timers PLL configuration Clock modulator...

  • Page 154

    CHAPTER 6 CLOCKS ■ Source clocks The following clock signals are the clock sources of the F2MC-16FX MCU. ● RC clock (CLKRC) The RC clock CLKRC is the output clock of the internal RC oscillator. The RC oscillator can generate two different clock frequencies (2MHz and 100kHz nominal, see datasheet) which can be selected with the RCFS (RC Clock Frequency Select) bit of the CKFCR register.

  • Page 155

    CHAPTER 6 CLOCKS clock divider 1 out of the System clock 1 (CLKS1). ● System clock 2 (CLKS2) The System clock 2 (CLKS2) is a second master clock which is never modulated. It feeds the clock divider for the Peripheral Clock 2 (CLKP2) only. Depending on the SC2S[1:0] (System Clock 2 Select) bits of the CKSR register, one of the following 4 clocks can be selected as the System clock 2: CLKRC (RC clock), CLKMC (Main clock), CLKPLL (unmodulated PLL clock) or CLKSC (Sub clock).

  • Page 156: Clock Control Registers

    CHAPTER 6 CLOCKS Clock Control Registers This section lists the clock control registers and describes the function of each register in detail. ■ Clock Control Registers Figure 6.2-1 Clock Control Registers shows an overview of all clock control registers Figure 6.2-1 Clock Control Registers CKSR: Clock Selection Register Address: (000400...

  • Page 157

    CHAPTER 6 CLOCKS 6.2.1 Clock Selection Register (CKSR) The Clock Selection Register (CKSR) is used to control the System Clock selector 1 and 2 and the oscillation circuits. ■ Configuration of the Clock Selection Register (CKSR) Figure 6.2-2 shows the configuration of the Clock Selection Register (CKSR) and Table 6.2-1 describes the function of each bit.

  • Page 158

    CHAPTER 6 CLOCKS Table 6.2-1 Function Description of Each Bit of the Clock Selection Register (CKSR) (1/3) Bit name Function bit 8 - SC1S0 and SC1S1: • These bits control the System Clock 1 Selector for the source of the Bus clock and the bit 9 System Clock 1 Peripheral clock 1 according to the following table:...

  • Page 159

    CHAPTER 6 CLOCKS Table 6.2-1 Function Description of Each Bit of the Clock Selection Register (CKSR) (2/3) Bit name Function bit 12 RCE: • This bit is used to enable/stop the internal RC oscillator. RC Clock Enable • Writing "1" to this bit enables the RC oscillator and writing "0" stops the oscillator. •...

  • Page 160

    CHAPTER 6 CLOCKS Table 6.2-1 Function Description of Each Bit of the Clock Selection Register (CKSR) (3/3) Bit name Function bit 15 SCE: • This bit is used to enable/stop the Sub oscillation circuit. Sub Clock Enable • Writing "1" to this bit enables the Sub oscillator and writing "0" stops the oscillator. •...

  • Page 161

    CHAPTER 6 CLOCKS 6.2.2 Clock Monitor Register (CKMR) The Clock Monitor Register (CKMR) is used to check the current status of the System clocks (Clock mode) and the status of the oscillation circuits. ■ Configuration of the Clock Monitor Register (CKMR) Figure 6.2-3 shows the configuration of the Clock Monitor Register (CKMR) and Table 6.2-2 describes the function of each bit.

  • Page 162

    CHAPTER 6 CLOCKS Table 6.2-2 Function Description of Each Bit of the Clock Monitor Register (CKMR) (1/2) Bit name Function bit 8 - SC1M0 and • These bits indicate which clock is currently used for the System Clock 1 according to bit 9 SC1M1: the following table:...

  • Page 163

    CHAPTER 6 CLOCKS Table 6.2-2 Function Description of Each Bit of the Clock Monitor Register (CKMR) (2/2) Bit name Function bit 13 MCM: • This bit indicates if the main oscillator is ready or not. Main Clock • MCM = "1" means that the main oscillator is ready and can be used. If MCM = "1" Monitor bit although MCE was set to "0", then the Main oscillator has not been disabled because the Main clock or PLL clock is used for System Clock 1 or 2.

  • Page 164

    CHAPTER 6 CLOCKS 6.2.3 Clock Stabilization Select Register (CKSSR) The Clock Stabilization Select Register (CKSSR) is used to select the stabilization times for the oscillation circuits, the PLL and for controlling the feedback resistors of the Main and Sub oscillation circuits. ■...

  • Page 165

    CHAPTER 6 CLOCKS Figure 6.2-4 Configuration of the Clock Stabilization Select Register (CKSSR) Initial value Address: 000402 1 1 1 1 1 1 1 1 MCST2 MCST1 MCST0 SRFBE MRFBE PCST SCST1 SCST0 R/W R/W R/W R/W R/W R/W R/W R/W bit2 bit1 bit0...

  • Page 166

    CHAPTER 6 CLOCKS Table 6.2-3 Function Description of Each Bit of the Clock Stabilization Select Register (CKSSR) (1/2) Bit name Function bit 0 - MCST0 to MCST2: • These bits select the stabilization time for the Main oscillation circuit according to the bit 2 Main Clock following table:...

  • Page 167

    CHAPTER 6 CLOCKS Table 6.2-3 Function Description of Each Bit of the Clock Stabilization Select Register (CKSSR) (2/2) Bit name Function bit 5 PCST: • This bits selects the stabilization time for the PLL clock according to the following PLL Clock table: Stabilization Time bit5...

  • Page 168

    CHAPTER 6 CLOCKS 6.2.4 Clock Frequency Control Register (CKFCR) The Clock Frequency Control Register (CKFCR) is used to control the Peripheral clock dividers (1 and 2), the Bus clock divider and the RC oscillator frequency. ■ Configuration of the Clock Frequency Control Register (CKFCR) Figure 6.2-5 shows the configuration of the Clock Frequency Control Register (CKFCR) and Table 6.2-4 describes the function of each bit.

  • Page 169

    CHAPTER 6 CLOCKS Table 6.2-4 Function Description of Each Bit of the Clock Frequency Control Register (CKFCR) (1/2) Bit name Function bit 0 RCFS: • This bit is used to set the clock frequency of the internal RC oscillator. RC Clock •...

  • Page 170

    CHAPTER 6 CLOCKS Table 6.2-4 Function Description of Each Bit of the Clock Frequency Control Register (CKFCR) (2/2) Bit name Function bit 12 - PC2D0 to PC2D3: • These bits control the clock divider for the Peripheral clock (CLKP2) according to bit 15 Peripheral Clock 2 the following table:...

  • Page 171

    CHAPTER 6 CLOCKS 6.2.5 PLL and clock frequency Control Register (PLLCR) The PLL and clock frequency Control Register (PLLCR) is used to control all functions of the PLL multiplier circuit and to control the Peripheral Clock Divider of CLKP3. ■ Configuration of the PLL and clock domain 3 frequency Control Register (PLLCR) Figure 6.2-6 show the configuration of the PLL and clock domain frequency 3 Control Registers (PLLCR) and Table 6.2-5 describes the function of each bit.

  • Page 172

    CHAPTER 6 CLOCKS Figure 6.2-6 Configuration of the PLL Control Register (PLLCR) Address: Initial value 000406 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 PC3D3 PC3D2 PC3D1 PC3D0 VMS2 VMS1 VMS0 PMS4 PMS3 PMS2 PMS1 PMS0 000407 R/W R/W R/W...

  • Page 173

    CHAPTER 6 CLOCKS Table 6.2-5 Function Description of Each Bit of the PLL Control Register (PLLCR) (1/2) Bit name Function bit 0 - PMS0 to PMS4: • These bits control the PLL clock multiplier factor according to the following table: bit 4 PLL clock bit4...

  • Page 174

    CHAPTER 6 CLOCKS Table 6.2-5 Function Description of Each Bit of the PLL Control Register (PLLCR) (2/2) Bit name Function bit 8- PC3D0 to PC3D3: For devices that do support CLKP3 bit 11 Peripheral Clock 3 • These bits control the clock divider for the Peripheral clock (CLKP3) according to Division select bits the following table: bit11...

  • Page 175

    CHAPTER 6 CLOCKS 6.2.6 Clock Input and LVD Control Register (CILCR) The Clock Input and LVD Control Register (CILCR) is used to control additional functions of the oscillator circuit and the Low Voltage Detection Level. ■ Configuration of the Clock Input and LVD Control Register (CILCR) Figure 6.2-7 shows the configuration of the Clock Input and LVD Control Registers (CILCR) and Table 6.2-6 describes the function of each bit.

  • Page 176

    CHAPTER 6 CLOCKS Table 6.2-6 Function Description of Each Bit of the Clock Input and LVD Control Register (CILCR) Bit name Function bit 8 - LVL0 to LVL3: • These bits control the analog threshold level for the Low Voltage Detector (LVD): bit 11 Low Voltage Detector Level...

  • Page 177: Clock Modes

    CHAPTER 6 CLOCKS Clock Modes Four clock modes are provided: RC clock mode, Main clock mode, PLL clock mode and Sub clock mode. ■ Definition of clock modes The clock mode of the MCU is defined by the source for the System clock 1 (CLKS1) which is selected by the SC1S[1:0] bits.

  • Page 178

    CHAPTER 6 CLOCKS used for the System clock 2, the watchdog or clock stop detect function. Disabling these clocks also disables the corresponding source clock timers. ■ Clock source switching Clock source switching means changing the clock source for CLKS1 or CLKS2. ●...

  • Page 179

    CHAPTER 6 CLOCKS the corresponding enable bit in the CKSR register to "1". After stabilization of the activated clock, the corresponding Clock monitor bit of the CKMR register is set and indicates the clock as "ready". • The Main clock must be enabled if the PLL clock should be enabled (The setting of PCE has no effect when MCE is set to "0").

  • Page 180: Configuration Of The Pll

    CHAPTER 6 CLOCKS Configuration of the PLL The PLL multiplier circuit is used to generate the PLL clock out of the Main clock. 32 different multiplier values (mul-1 to mul-32) are available. ■ Components of the PLL clock multiplier circuit The following block diagram describes the modules of the PLL.

  • Page 181

    CHAPTER 6 CLOCKS ● "1/n divider" (PLL clock divider) The "1/n divider" is controlled by the PMS[4:0] PLL clock Multiplier Select bits. It defines the frequency multiplication value of the PLL clock multiplier circuit (relation between CLKMC and CLKPLL). Multiplication values from 1 to 32 are available. However the minimum and maximum permitted frequencies for CLKMC, CLKVCO and CLKPLL (->CLKS1/S2) must be adhered.

  • Page 182

    CHAPTER 6 CLOCKS Table 6.4-1 Recommended settings for the PMS[3:0], VMS[2:0] bits (2/2)for CLKMC=4MHz Main Requested Setting for Setting for Oscillation PLL output PMS[4:0] bits VMS[2:0] bits output frequency frequency (n division (m division frequency CLKMC CLKPLL value) value) CLKVCO 4 MHz 88 MHz "10101"...

  • Page 183: Oscillation Stabilization Wait Time

    CHAPTER 6 CLOCKS Oscillation Stabilization Wait Time When the power is turned on, when stop mode is released or when a disabled clock is enabled, an oscillation stabilization wait time is required before the clock can be used. ■ Oscillation Stabilization Wait Interval Ceramic and crystal oscillators which can be connected to the X0/X1 and X0A/X1A pins generally require several ms to stabilize at their natural frequency (oscillation frequency) when oscillation starts.

  • Page 184

    CHAPTER 6 CLOCKS Figure 6.5-1 Operation Immediately after Oscillation Starts Oscillator-activated Oscillation stabilization Clock can be used oscillation time wait interval as System clock X1/X1A Start of oscillation Stable oscillation Clock ready flag set ● RC clock stabilization interval The RC clock stabilization time is fixed to 64 RC clock cycles. However after a Power reset or an External reset (RST falling edge), an additional wait time of 700 RC clock cycle (Power reset) or 700 RC clock cycles (External reset) is applied by the reset extension circuit (see section 8.3 Startup after Power and External reset for more details).

  • Page 185: Connection Of An Oscillator Or An External Clock To The Microcontroller

    Fast Clock Input feature). This feature is activated by setting the CILCR:FCI bit to ’1’ before switching the device to the external Main clock. Fujitsu recommends to always use the Fast Clock Input feature when connecting an external clock to the Main oscillator.

  • Page 186

    CHAPTER 6 CLOCKS Figure 6.6-2 Example of Connecting an External Clock to the Microcontroller MC-16FX MCU X0(X0A) X1(X1A) Open...

  • Page 187: Clock Modulator

    Clock Modulator. The clock modulator is currently being evaluated and should not be used for other purpose than testing. 7.1 "Overview" 7.2 "Register Description" 7.3 "Application Note" THIS FUNCTION IS UNDER EVALUATION AND MAY NOT BE USED. PLEASE CONTACT FUJITSU.

  • Page 188

    CHAPTER 7 CLOCK MODULATOR MB96300 Super Series Hardware Manual Overview This section describes an overview of the Clock Modulator. ■ Overview The clock modulator is intended for the reduction of electromagnetic interference - EMI, by spreading the spectrum of the clock signal over a wide range of frequencies. The module is fed with an unmodulated reference clock with frequency F0, provided by the PLL circuit.

  • Page 189: Register Description

    MB96300 Super Series Hardware Manual CHAPTER 7 CLOCK MODULATOR Register Description This section lists the clock modulator registers and describes the function of each register in detail. ■ Clock modulator registers Figure 7.2-1 Clock modulator registers CMCR: Clock Modulator Control Register Address: 000418 MOD- MODEN PDX...

  • Page 190

    CHAPTER 7 CLOCK MODULATOR MB96300 Super Series Hardware Manual 7.2.1 Clock Modulator Control Register (CMCR) The Control Register (CMCR) has the following functions: • Set the modulator to power down mode • Modulator enable/disable • Indicates the status of the modulator ■...

  • Page 191

    MB96300 Super Series Hardware Manual CHAPTER 7 CLOCK MODULATOR ■ Clock modulator control register contents Table 7.2-1 Function of each bit of the clock modulator control register (1/2) Bit name Function bit 0 PDX: "0": Power down mode Power down bit "1": Power up •...

  • Page 192

    CHAPTER 7 CLOCK MODULATOR MB96300 Super Series Hardware Manual Table 7.2-1 Function of each bit of the clock modulator control register (2/2) Bit name Function bit 2 MODRUN: "0": MCU is running with unmodulated clock Modulator status "1": MCU is running with modulated clock •...

  • Page 193

    MB96300 Super Series Hardware Manual CHAPTER 7 CLOCK MODULATOR 7.2.2 Clock Modulation Parameter Register (CMPR) The Clock Modulation Parameter Register (CMPR) determines the modulation degree. ■ Clock Modulation parameter register Figure 7.2-3 Clock Modulation parameter register CMPRL: Clock Modulator Parameter Register (lower) Address: 00041A R/W R/W R/W R/W R/W...

  • Page 194

    CHAPTER 7 CLOCK MODULATOR MB96300 Super Series Hardware Manual Frequency of unmodulated input clock (PLL frequency) Period of unmodulated input clock (PLL clock period) resolution: resolution of frequencies in the modulated clock. low (1) to high (7) minimal frequency occurring in the modulated clock maximal frequency occurring in the modulated clock phase skew: The maximal phase shift of the modulated clock relative to the unmodulated...

  • Page 195

    MB96300 Super Series Hardware Manual CHAPTER 7 CLOCK MODULATOR Table 7.2-4 Modulation Parameter recommended settings (2/2) F0 (MHz) resolution (MHz) +/- phase +/- phase CMPR degree skew skew (MHz) min/max [periods] [periods] 12.8 21.3 1.5625 4.0625 04AC 11.63 25.6 3.125 7.4375 04EA 13.47...

  • Page 196: Application Note

    CHAPTER 7 CLOCK MODULATOR MB96300 Super Series Hardware Manual Application Note This chapter describes the startup/stop sequence of the clock modulator and the modulation parameter settings. ■ Recommended startup/stop sequence start Switch modulator from power down to power up mode: Set PDX=1 Switch on PLL Wait PLL lock time (refer to the CKMR:PCM bit).

  • Page 197

    MB96300 Super Series Hardware Manual CHAPTER 7 CLOCK MODULATOR if the EMI measurements does not fulfill the requirements, you may either reduce the modulation degree at the same e.g. resolution: 7, degree: 1, CMPR = frequency resolution 0x3F9 (this may improve the reduction in the upper frequency band >...

  • Page 198

    CHAPTER 7 CLOCK MODULATOR MB96300 Super Series Hardware Manual...

  • Page 199: Resets And Startup

    CHAPTER 8 RESETS AND STARTUP This chapter describes the resets and the startup of for the F2MC-16FX family microcontrollers. 8.1 "Resets" 8.2 "Reset, System clock and Stabilization Wait Times" 8.3 "Startup after Power and External reset" 8.4 "Boot ROM program execution and Operation mode and ROM Configuration Block"...

  • Page 200: Resets

    CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Resets If a reset is generated, the CPU immediately stops the current execution process and waits for the reset to be cleared. The CPU then begins with the Boot ROM program execution.

  • Page 201

    MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP ● Power reset A power reset is generated when the power is turned on with a power on rise time as specified in the datasheet (power-on reset) or when the low voltage detector detects that the power supply Vcc falls below a certain value as specified in the LVL bits of the CILCR register (low voltage reset).

  • Page 202

    CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual The contents of internal RAM and all registers which are not reset (initial value ’X’) is maintained. Note: *1: Except for bytes at addresses 7FFC-7FFF. The contents of the registers in the GPR bank 00 and 01 as well as the 4 above mentioned RAM bytes are undefined after each reset.

  • Page 203: Reset, System Clock And Stabilization Wait Times

    MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP Reset, System clock and Stabilization Wait Times The F2MC-16FX family has five reset causes. The System clocks (CLKS1 and CLKS2) are set to RC clock after each reset. The stabilization wait time depends on the reset cause and the status of the RC oscillator when the reset occurs.

  • Page 204

    CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual ● External reset asserted for less than 700 RC clock cycles The External reset extension time is not expired in this case. Hence the execution of the Boot ROM program by the CPU is delayed until the External reset extension time plus the RC clock stabilization time of 64 RC clock cycles is expired.

  • Page 205: Startup After Power And External Reset

    MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP Startup after Power and External reset After a Power or External reset event, the MCU waits for the stabilization of the power supply and the RC oscillator. Then the MCU starts executing the Boot ROM program with the RC clock as clock source (RC Run mode).

  • Page 206

    CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Figure 8.3-1 Block diagram of reset extension circuit CLKRC Clock Power reset extension counter (10bit) PRST Power-on event Init Low voltage event CLKRC Clock Power-on event External reset extension counter (10bit) Init Low voltage event falling edge detection...

  • Page 207

    MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP the Main clock timer is activated 700 RC clock cycles after a RST falling edge or 700 RC clock cycles after clearing a power-on or low voltage event. Thus the Main oscillation stabilization wait time takes place even if RST is still asserted.

  • Page 208: Boot Rom Program Execution And Operation Mode And Rom Configuration Block

    CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Boot ROM program execution and Operation mode and ROM Configuration Block When the reset signal is released, the MCU starts with the execution of the internal Boot ROM program. The Boot ROM program reads the status of the mode pins (MD2-MD0), which define the operation mode of the MCU.

  • Page 209

    MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP Table 8.4-1 Mode Pin settings Mode pin setting Configuration of Operation mode Boot Vector external bus for Remarks name Source Boot Vector read access Serial Used for serial Flash Communication programming mode Internal Vector...

  • Page 210

    CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual The Internal Vector mode is available for all MCU types and the fixed Boot Vector is given by DF0080 ● Serial Communication mode (MD[2:0]="010") This mode allows the reading and writing of any memory address by serial communicated read/write commands.

  • Page 211

    MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP Table 8.4-2 Structure of Main ROM Configuration Block (MRCB) Offset Sub-block Marker Comment MFSB Secure Flash by 99 Reserved MFSUK Unlock key for secured Flash Security and Protection reserved configuration block MFMWPAM Activation of write protection by 292D3A7B MFMWPSM...

  • Page 212

    CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual ■ Function description of RCB Markers ● Security and Protection Configuration Block (SPCB) The read security feature prevents the unauthorized read-out of Flash contents and targets all cases other than read access by application in Internal Vector mode.

  • Page 213

    MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP Figure 8.4-2 Configuration of the UART Scan Deactivation Marker Address: DF0034 : USDM0 (lower word) DF0036 : USDM1 (upper word) USDM0 USDM1 When the content of {USDM1, USDM0} = 292D3A7BH, then no temporary UART scanning is performed. For any other value of {USDM1, USDM0}, the Boot ROM will scan dedicated UART channels for limited time after main reset.

  • Page 214

    CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual ■ Flowchart Internal Vector Mode Figure 8.4-4 Boot ROM sequence in Internal Vector Mode Internal Vector Mode not protected (M/S)FMWPAM Main Reset ? set ? write protected Write FMWC USDM set? configuration Scan UART MFSB or...

  • Page 215

    MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP ■ Flowchart in External Vector Mode Figure 8.4-5 Boot ROM sequence in External Vector Modes External External External Vector Mode 0 Vector Mode 1 Vector Mode 2 Get configuration Get configuration Get configuration 8bit multiplex 16bit multiplex...

  • Page 216: Reset Control Registers

    CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Reset Control Registers This section lists the Reset Control Registers and describes the function of each register in detail. ■ Reset Control Registers The Reset Controller has two registers, the Reset Configuration Register (RCR) and the Reset Cause and Clock status Register (RCCSR/RCCSRC).

  • Page 217

    MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP 8.5.1 Reset Configuration Register (RCR) The Reset Configuration Register (RCR) is used to assert a Software reset, configure the low voltage reset and detector and to configure the Clock stop detection circuit. ■...

  • Page 218

    CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Figure 8.5-2 Configuration of the Reset Configuration Register (RCR) Address: Initial value 00040C X X 0 0 0 1 1 0 LVDE LVRE SRSTG SCSDI MCSDI CSDRE R/W R/W R/W R/W R/W bit0 SRSTG...

  • Page 219

    MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP Table 8.5-1 Function Description of Each Bit of the Reset Configuration Register (RCR) (2/3) Bit name Function bit 1 LVRE: • This bit controls the Low voltage reset function which is one reset cause of the Power Low Voltage Reset reset.

  • Page 220

    CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Table 8.5-1 Function Description of Each Bit of the Reset Configuration Register (RCR) (3/3) Bit name Function bit 5 SCSDI: • This bit controls the measurement interval of the Sub clock stop detection circuit. Sub Clock Stop •...

  • Page 221

    MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP 8.5.2 Reset Cause and Clock Status Register (RCCSR/ RCCSRC) The RCCSR/RCCSRC register shows the reset cause and the status of the Main and Sub clock ■ Configuration of the Reset Cause and Clock Status Register (RCCSR/RCCSRC) The Reset Cause and Clock Status Register (RCCSR/RCCSRC) can be accessed at two addresses.

  • Page 222

    CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Figure 8.5-3 Configuration of the Reset Cause and Clock Status Register (RCCSR/RCCSRC) Initial value X X X X X X X X Address: SCMF MCMF WRST SRST SCRST MCRST ERST PRST 00040B (RCCSRC) R/C R/C R/C R/C R/C...

  • Page 223

    MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP Table 8.5-2 Function Description of the Bits of the Reset Cause and Clock Status Register (RCCSR) (1/2) Bit name Function bit 8 PRST: • This bit indicates if a Power reset was generated. Power Reset •...

  • Page 224

    CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Table 8.5-2 Function Description of the Bits of the Reset Cause and Clock Status Register (RCCSR) (2/2) Bit name Function bit 14 MCMF: • This bit indicates if a missing Main clock was detected. Main Clock •...

  • Page 225

    MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP address 00040B . Any bit corresponding to a reset cause that has already been generated is not cleared when another reset is generated (a setting of "1" is retained). After a Power reset, the register should be cleared by reading in order to initialize all bits. Note: If the power is turned on under conditions where power-on reset may not occur (power-on profile as specified in the datasheet not met), the value in RCCSR register is not guaranteed.

  • Page 226

    CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual 8.5.3 Clock Input and LVD Control Register (CILCR) The Clock Input and LVD Control Register (CILCR) is used to control additional functions of the oscillator circuit and the Low Voltage Detection Level. ■...

  • Page 227

    MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP Table 8.5-4 Function Description of Each Bit of the Clock Input and LVD Control Register (CILCR) Bit name Function bit 8 - LVL0 to LVL3: • These bits control the analog threshold level for the Low Voltage Detector (LVD): bit 11 Low Voltage Detector Level...

  • Page 228: Operation Of The Clock Stop Detection Function And Reset

    CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Operation of the Clock stop detection function and reset This section describes the operation of the clock stop detection circuit that detects a failure of the external Main or Sub oscillator. ■...

  • Page 229

    MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP Table 8.6-1 Clock stop detection interval Clock Stop Detection Interval RC clock Time for RC clock Time for RC clock Observed Select cycles frequency of frequency of Setting clock 2MHz (min - max) / 100kHz (min - max) (minimum / (minimum...

  • Page 230

    CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual ● Activation of the Clock stop detection reset The Clock stop detection reset is enabled by setting the RCR: CSDRE bit to "1". ● Generating a Clock stop detection reset A Clock stop detection reset is generated in the following cases.

  • Page 231

    MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP ● Stop mode All oscillators including the RC oscillator are disabled in Stop mode, hence no clock stop detection is possible. If an interrupt is asserted in Stop mode, then the MCU changes to Run mode with the clocks specified in the CKSR register.

  • Page 232: Operation Of The Low Voltage Reset Function

    CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual Operation of the low voltage reset function This section describes the operation of the low voltage reset function. ■ Function of the low voltage reset The low voltage reset function is using the low voltage detector that compares the power supply voltage V with an internally generated reference voltage.

  • Page 233

    MB96300 Super Series Hardware Manual CHAPTER 8 RESETS AND STARTUP ● Effect on current consumption The low voltage detector draws a current when it is activated (see datasheet for details). This current flows independent of the selected operation mode. If this is not acceptable when using standby modes, disable the low voltage detector and reset before changing to standby mode.

  • Page 234

    CHAPTER 8 RESETS AND STARTUP MB96300 Super Series Hardware Manual...

  • Page 235: Standby Mode And Voltage Regulator Control Circuit

    CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT This chapter explains the functions and operations of the standby mode control circuit and the control of the internal voltage regulator. The regulator control can be used to optimize power consumption, especially in standby modes. 9.1 "Overview of the CPU Operating Modes"...

  • Page 236: Overview Of The Cpu Operating Modes

    CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series Overview of the CPU Operating Modes The F MC-16FX MCU has the following CPU operating modes: • Run mode • Sleep mode • Timer mode • Stop mode Sleep mode, Timer mode and Stop mode are called Standby modes.

  • Page 237

    MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Figure 9.1-1 CPU operating mode and current consumption Current consumption Several tens of mA PLL Run mode PLL Sleep mode Main Run mode Main Sleep mode PLL Timer mode RC Run mode RC Sleep mode Main Timer mode...

  • Page 238

    CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series Figure 9.1-2 Mode change diagram Reset reset release & RC clock ready SC1S=00 & SC1S=01 & SC1S=10 & SC1S=11 & SC1M!=00 SC1M!=01 SC1M!=10 SC1M!=11 RC clock ready Main clock ready PLL clock ready Sub clock ready RC Run...

  • Page 239

    MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL peripheral functions. Independent clock dividers for the Bus clock operating the CPU (CLKB) and the Peripheral clock 1 operating most peripheral functions (CLKP1) are fed by the Main clock and allow flexible frequency settings.

  • Page 240

    CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series selector. The status of the PLL multiplier circuit, the RC and Sub oscillator depend on the setting of the PCE, RCE and SCE bits when they are not used as System clock 2. ●...

  • Page 241

    MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Note: The different Timer modes may have the same behavior if more than one of the PCE, MCE, SCE and RCE bits is set to "1". However, the run mode that the device transits to, upon wakeup from timer mode by interrupt, depends on which of the four timer modes the device was in.

  • Page 242: Standby Mode Control Register (smcr)

    CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series Standby Mode Control Register (SMCR) This register switches to standby mode, controls the pin functions in Timer and Stop mode and sets the voltage regulator to Low Power mode. ■...

  • Page 243

    MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Table 9.2-1 Function description of each bit of the standby mode control register (SMCR) Bit name Function bit 0 - SMS0 and SMS1: • These bits request switching to a Standby mode according to the following table: bit 1 Standby Mode Select bit1...

  • Page 244

    ~40µs for switching the regulator back to High Power Mode or Low Power Mode A Note: Do not change this bit, because this function is currently under evaluation by Fujitsu. bit 6 - Reserved • Always write "0" to these bits.

  • Page 245: Voltage Regulator Control Register (vrcr)

    MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Voltage Regulator Control Register (VRCR) The voltage regulator control register defines the output voltage of the internal Voltage Regulator in different operation modes ■ Voltage Regulator Control Register (VRCR) Figure 9.3-1 shows the configuration of the Voltage Regulator Control Register (VRCR) and Table 9.3-1 describes the function of each bit.

  • Page 246

    Sub Timer mode) when the Main and RC oscillators are both disabled. It can also be selected with the SMCR:LPMS and LPMSS bits under certain conditions. Note: Do not change these bits, because permitted settings are currently under evaluation by Fujitsu.

  • Page 247

    MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Table 9.3-1 Function Description of Each Bit of the Voltage Regulator Control Register (VRCR) (2/2) Bit name Function bit 6 - HPM0 to HPM1: • These bits select the output voltage of the regulator in High Power Mode according to bit 7 High Power Mode the following table:...

  • Page 248: Standby Modes

    CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series Standby Modes The standby modes include the Sleep (RC Sleep, Main Sleep, PLL Sleep, Sub Sleep), Timer (RC Timer, Main Timer, PLL Timer, Sub Timer) and Stop modes.

  • Page 249

    MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL ■ Operation status during standby mode Table 9.4-1 "Operation status during standby mode" shows the status of the clocks, CPU, Peripherals and external pins for the different standby modes. Table 9.4-1 Operation status during standby mode Condition Main...

  • Page 250

    CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series 9.4.1 Sleep mode (RC Sleep, Main Sleep, PLL Sleep, Sub Sleep mode) This mode causes the CPU operating clock (Bus clock CLKB) to stop while other components continue to operate. Transition to Sleep mode is done by writing to the standby mode control register (SMCR).

  • Page 251

    MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Note: To make sure instructions following the SMS write instruction are executed after wakeup from Sleep mode (and not before transition to Sleep mode), poll the SMS bits after setting to "01". Branch to the next instruction only when the SMS bits are cleared to "00".

  • Page 252

    CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series Figure 9.4-1 Release of the Sleep Mode by External Reset RST Pin Sleep mode RC clock Depends on RCE bit Oscillating Main clock Depends on MCE bit Oscillating PLL clock Depends on PCE bit Stopped...

  • Page 253

    MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL 9.4.2 Timer Mode (RC Timer, Main Timer, PLL Timer, Sub Timer mode) This mode causes all functions, excluding oscillators, PLL and source clock timers, to stop. Transition to Timer mode is done by writing to the standby mode control register (SMCR).

  • Page 254

    CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series Note: To make sure instructions following the SMS write instruction are executed after wakeup from Timer mode (and not before transition to Timer mode), poll the SMS bits after setting to "10". Branch to the next instruction only when the SMS bits are cleared to "00".

  • Page 255

    MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Figure 9.4-3 Release of the Timer Mode by External Reset RST Pin Timer mode RC clock Depends on RCE bit Oscillating Main clock Depends on MCE bit Oscillating PLL clock Depends on PCE bit...

  • Page 256

    CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series 9.4.3 Stop Mode Because this mode causes all oscillators to stop and inactivates all functions, data can be retained by the lowest power consumption. ■ Functions in Stop Mode ●...

  • Page 257

    MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Note: Setting the SMS bits to "11" (Stop mode) is allowed together with changing the clock mode (by writing a new value to the SC1S or SC2S System Clock Select bits of the CKSR register). The new clock setting becomes effective immediately after leaving the Stop mode.

  • Page 258

    CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series Figure 9.4-5 Release of the Stop Mode by External Reset RST Pin Stop mode RC clock Stopped Oscillating Main clock Stopped Oscillating PLL clock Stopped Stopped Sub clock Stopped Oscillating CPU clock...

  • Page 259: Mode Change Table And Operation Status

    MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Mode Change Table and operation status Table 9.5-1 show the mode change table of the F MC-16FX MCU and Table 9.5-2 shows the operation status in each operating mode. ■...

  • Page 260

    CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series ■ Operation status in each operating mode Table 9.5-2 lists the operation status in each operating mode. Table 9.5-2 Operation status in each operating mode RC oscillator Main Clock Clock source for Operation...

  • Page 261: Usage Notes On Standby Mode

    MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Usage Notes on Standby Mode Note the following items when using the standby modes: • Switching to a standby mode and Interrupt • Release of the standby mode by an Interrupt •...

  • Page 262

    CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series Note: After Stop mode release, the CPU starts operating after stabilization of the System clock 1 selected by the SC1S bit. However another clock can be selected as System clock 2 with a longer stabilization time. If the CPU tries to access a peripheral resource clocked by the Peripheral clock 2, then the CPU will be put into hold state until CLKP2 is stabilized and the access can be completed.

  • Page 263: Voltage Regulator Operation

    MB96300 Super Series Hardware Manual CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL Voltage Regulator Operation The 16FX MCUs are equipped with an on-chip voltage regulator which generates the power supply for the core logic out of the external power supply. This regulator has different operation modes with programmable output voltage.

  • Page 264

    CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series 9.7.1 Changing the Voltage Regulator operation mode The voltage regulator operation modes are automatically controlled by hardware depending on the selected CPU operation mode. However in some modes and under certain conditions, it is permitted to manually change the regulator from High Power mode to Low Power mode for further current saving.

  • Page 265

    Switching to the Low Power mode B with the SMCR:LPMBSS bit Note: Do not change this bit, because this function is under evaluation by Fujitsu. Setting the SMCR:LPMBSS bit to "1" switches the voltage regulator to the Low Power mode B instead of Low Power mode A after the next transition to a Standby mode.

  • Page 266

    CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series ■ Permitted configurations for using the Low Power mode of the voltage regulator The voltage regulator can be switched to the Low Power mode (setting SMCR:LPMS or LMPSS to "1") in the following configurations: Table 9.7-1 Permitted configurations for using the Low Power mode A Operation...

  • Page 267

    The default output voltage of the regulator in Low Power mode A and B is 1.8V. ● Changing the Core voltage in Low Power mode A Changing the output voltage of the regulator in the Low Power mode A is not approved by Fujitsu. ● Changing the Core voltage in Low Power mode B For applications which require a small current consumption in Stop mode, it is possible to reduce the core voltage to 1.2V by setting the VRCR:LPMB[2:0] bits to "000"...

  • Page 268

    CHAPTER 9 STANDBY MODE AND VOLTAGE REGULATOR CONTROL CIRCUIT MB96300 Super Series...

  • Page 269: Source Clock Timers

    CHAPTER 10 SOURCE CLOCK TIMERS This chapter explains the functions and operations of the three source clock timers (RC clock timer, Main clock timer and Sub clock timer). 10.1 "Overview" 10.2 "RC Clock Timer" 10.3 "Main Clock Timer" 10.4 "Sub Clock Timer"...

  • Page 270

    CHAPTER 10 SOURCE CLOCK TIMERS MB96300 Super Series Hardware Manual 10.1 Overview The MB96300 Super series offers 3 independent source clock timers (RC clock timer, Main clock timer and Sub clock timer) which can issue interrupts at specified intervals and which are used to measure the oscillation stabilization time. ■...

  • Page 271: Rc Clock Timer

    MB96300 Super Series Hardware Manual CHAPTER 10 SOURCE CLOCK TIMERS 10.2 RC Clock Timer The RC clock timer consists of a 23-bit counter and a control register. The 23-bit counter divides the RC clock CLKRC. The RC clock timer issues interrupts at specified intervals based on carry signals of the RC clock counter.

  • Page 272

    CHAPTER 10 SOURCE CLOCK TIMERS MB96300 Super Series Hardware Manual 10.2.1 RC Clock Timer Control Register (RCTCR) The RC Clock Timer Control Register (RCTCR) is used to control the RC clock timer interval interrupt function and to reset the RC clock timer. ■...

  • Page 273

    MB96300 Super Series Hardware Manual CHAPTER 10 SOURCE CLOCK TIMERS Figure 10.2-2 Configuration of the RC Clock Timer Control Register (RCTCR) Address: Initial value 000408 X 0 0 1 0 0 0 0 RCTI2 RCTI1 RCTI0 RCTIE RCTIF RCTR RCTI3 R/W R/W R/W R/W R/W bit3...

  • Page 274

    CHAPTER 10 SOURCE CLOCK TIMERS MB96300 Super Series Hardware Manual Table 10.2-1 Function Description of Each Bit of the RC Clock Timer Control Register (RCTCR) Bit name Function bit 0 - RCTI0 to RCTI3: • These bits control the RC clock timer interrupt interval according to the following bit 3 RC Clock Timer table:...

  • Page 275

    MB96300 Super Series Hardware Manual CHAPTER 10 SOURCE CLOCK TIMERS 10.2.2 Operations of RC Clock Timer The RC clock timer functions as an interval timer for generating interrupts at specified intervals. ■ RC clock counter The RC clock counter consists of a 23-bit counter that is clocked with the RC clock CLKRC. When the RC clock is active, the RC clock counter always keeps counting.

  • Page 276: Main Clock Timer

    CHAPTER 10 SOURCE CLOCK TIMERS MB96300 Super Series Hardware Manual 10.3 Main Clock Timer The Main clock timer consists of a 23-bit counter and a control register. The 23-bit counter divides the Main clock CLKMC. The Main clock timer issues interrupts at specified intervals based on carry signals of the Main clock counter.

  • Page 277

    MB96300 Super Series Hardware Manual CHAPTER 10 SOURCE CLOCK TIMERS 10.3.1 Main Clock Timer Control Register (MCTCR) The Main Clock Timer Control Register (MCTCR) is used to control the Main clock timer interval interrupt function and to reset the Main clock timer. ■...

  • Page 278

    CHAPTER 10 SOURCE CLOCK TIMERS MB96300 Super Series Hardware Manual Figure 10.3-2 Configuration of the Main Clock Timer Control Register (MCTCR) Address: Initial value 000409 X 0 0 1 0 0 0 0 MCTI2 MCTI1 MCTI0 MCTIE MCTIF MCTR MCTI3 R/W R/W R/W R/W R/W bit11...

  • Page 279

    MB96300 Super Series Hardware Manual CHAPTER 10 SOURCE CLOCK TIMERS Table 10.3-1 Function Description of Each Bit of the Main Clock Timer Control Register (MCTCR) Bit name Function bit 8 - MCTI0 to MCTI2: • These bits control the Main clock timer interrupt interval according to the following bit 11 Main Clock Timer table:...

  • Page 280

    CHAPTER 10 SOURCE CLOCK TIMERS MB96300 Super Series Hardware Manual 10.3.2 Operations of Main Clock Timer The Main clock timer functions as an interval timer for generating interrupts at specified intervals and as a timer for waiting for the Main oscillation to stabilize. ■...

  • Page 281: Sub Clock Timer

    MB96300 Super Series Hardware Manual CHAPTER 10 SOURCE CLOCK TIMERS 10.4 Sub Clock Timer The Sub clock timer consists of a 17-bit counter and a control register. The 17-bit counter divides the Sub clock CLKSC. The Sub clock timer issues interrupts at specified intervals based on carry signals of the Sub clock counter.

  • Page 282

    CHAPTER 10 SOURCE CLOCK TIMERS MB96300 Super Series Hardware Manual 10.4.1 Sub Clock Timer Control Register (SCTCR) The Sub Clock Timer Control Register (SCTCR) is used to control the Sub clock timer interval interrupt function and to reset the Sub clock timer. ■...

  • Page 283

    MB96300 Super Series Hardware Manual CHAPTER 10 SOURCE CLOCK TIMERS Figure 10.4-2 Configuration of the Sub Clock Timer Control Register (SCTCR) Address: Initial value 00040A X 0 0 1 X 0 0 0 SCTI2 SCTI1 SCTI0 SCTIE SCTIF SCTR R/W R/W R/W R/W R/W bit2 bit1...

  • Page 284

    CHAPTER 10 SOURCE CLOCK TIMERS MB96300 Super Series Hardware Manual Table 10.4-1 Function Description of Each Bit of the Sub Clock Timer Control Register (SCTCR) Bit name Function bit 0 - SCTI0 to SCTI2: • These bits control the Sub clock timer interrupt interval according to the following bit 2 Sub Clock Timer table:...

  • Page 285

    MB96300 Super Series Hardware Manual CHAPTER 10 SOURCE CLOCK TIMERS 10.4.2 Operations of Sub Clock Timer The Sub clock timer functions as an interval timer for generating interrupts at specified intervals and as a timer for waiting for the Sub oscillation to stabilize. ■...

  • Page 286

    CHAPTER 10 SOURCE CLOCK TIMERS MB96300 Super Series Hardware Manual...

  • Page 287: Watchdog Timer And Watchdog Reset

    CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET This chapter explains the functions and operations of the Watchdog timer and reset. 11.1 "Outline of Watchdog Timer and Reset" 11.2 "Watchdog Timer Control Registers" 11.3 "Watchdog Timer Operation"...

  • Page 288: Outline Of Watchdog Timer And Reset

    CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET MB96300 Super Series Hardware Manual 11.1 Outline of Watchdog Timer and Reset The watchdog circuit consists of a 24-bit watchdog counter, control registers and the watchdog reset controller. The 24-bit watchdog counter uses either the RC clock, the Main clock or the Sub clock as clock source.

  • Page 289: Watchdog Timer Control Registers

    MB96300 Super Series Hardware Manual CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET 11.2 Watchdog Timer Control Registers This section lists the Watchdog Timer Control Registers and describes the function of each register in details. ■ Watchdog Timer Control Registers The Watchdog Timer has two control registers, the Watchdog Timer Configuration register (WDTC) and the Watchdog Timer Clear Pattern register (WDTCP).

  • Page 290

    CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET MB96300 Super Series Hardware Manual 11.2.1 Watchdog Timer Configuration register (WDTC) The Watchdog Timer Configuration register (WDTC) is used to select the clock source and the watchdog interval and to activate some special functions of the Watchdog Timer. ■...

  • Page 291

    MB96300 Super Series Hardware Manual CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET Figure 11.2-2 Configuration of the Watchdog Timer Configuration Register (WDTC) Address: Initial value 00040E X 0 0 0 0 0 0 0 WTI2 WTI1 WTI0 RSTP WTCS1 WTCS0 WTI3 R/W R/W R/W R/W R/W R/W R/W bit3...

  • Page 292

    CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET MB96300 Super Series Hardware Manual Table 11.2-1 Function Description of Each Bit of the Watchdog Timer Configuration register (WDTC) (1/2) Bit name Function bit 0 - WTI0 to WTI3: • These bits select the Watchdog Timer Interval according to the following table: bit 3 Watchdog Timer bit3...

  • Page 293

    MB96300 Super Series Hardware Manual CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET Table 11.2-1 Function Description of Each Bit of the Watchdog Timer Configuration register (WDTC) (2/2) Bit name Function bit 4 - WTCS0 to • These bits select the clock source for the Watchdog Timer according to the following bit 5 WTCS1: table:...

  • Page 294

    CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET MB96300 Super Series Hardware Manual 11.2.2 Watchdog Timer Clear Pattern register (WDTCP) The Watchdog Timer Clear Pattern register (WDTCP) is used to activate the Watchdog reset function and to clear the Watchdog counter. ■...

  • Page 295: Watchdog Timer Operation

    MB96300 Super Series Hardware Manual CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET 11.3 Watchdog Timer Operation The Watchdog timer and reset function can be used to detect a hang-up of the user program. If the Watchdog counter is not cleared within the specified time due to, for example, a program hang-up, the Watchdog timer resets the system.

  • Page 296

    CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET MB96300 Super Series Hardware Manual When the RC clock should be used as clock source and the system requires changing the RC clock frequency during operation, then set the WDTC: WTCS[1:0] bits to "00". Be aware that changing the RC clock frequency also changes the Watchdog Timer interval.

  • Page 297

    MB96300 Super Series Hardware Manual CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET Writing the same data as currently stored in the WDTCP register has no effect. Writing the complementary data of the current WDTCP contents clears the Watchdog counter and replaces the current value in the WDTCP register.

  • Page 298

    CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET MB96300 Super Series Hardware Manual • The RC clock frequency was changed although WDTC:WTCS was set to "01". • Transition to Stop mode was requested although WDTC:RSTP was set to ’1’.

  • Page 299: External Bus Interface

    CHAPTER 12 EXTERNAL BUS INTERFACE This chapter explains the functions and operations of the external bus interface. 12.1 "Outline of External Bus" 12.2 "External bus configuration registers" 12.3 "External Memory Access Control Signal Operation" 12.4 "Notes on using the external bus" 12.5 "External Boot Vector fetch"...

  • Page 300: Outline Of External Bus

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.1 Outline of External Bus The External Bus interface of the F MC-16FX MCU provides various access methods and access areas.

  • Page 301

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE 12.1.1 Features of the External Bus Interface This chapter summarizes the features of the External Bus Interface ■ Features of the External Bus Interface • 16 data lines • Up to 24 address lines (depending on the device) •...

  • Page 302

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.1.2 Terminology This chapter explains some basic terms of the External Bus Interface. ● Bus mode Bus mode means the mode for controlling the internal ROM operation and external access function. The bus mode depends on the EAE[5:0] and ERE bits of the External Bus Mode register (EBM).

  • Page 303

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE 12.1.3 External bus areas Up to 6 external bus areas with dedicated Chip select signals can be configured independently. The 16MB address area can be divided into 6 external address areas with corresponding Chip select signals.

  • Page 304

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.1.4 Memory Space in Each Bus Mode Figure 12.1-1 "Relationship between Access Areas and Physical Addresses for Each Bus Mode" shows the correspondence between the access areas and physical addresses for each bus mode.

  • Page 305

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE ■ Memory Space in Each Bus Mode Figure 12.1-1 Relationship between Access Areas and Physical Addresses for Each Bus Mode Single chip Internal ROM, external ROM, external bus external bus ff.ffff ROM/Flash ROM/Flash...

  • Page 306: External Bus Configuration Registers

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.2 External bus configuration registers The external bus contains various registers to change the external bus configuration for a wide range of external bus protocols: - External Bus Mode register (EBM) - External Bus Clock and Function register (EBCF) - External Bus Address output Enable register [2:0] (EBAE[2:0]) - External Bus Control Signal register (EBCS)

  • Page 307

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE ■ Overview of External bus configuration registers Figure 12.2-1 External bus configuration registers External Bus Mode register Initial value address: 0006F0 EAE5 EAE4 EAE2 EAE3 EAE1 EAE0 00000000 External Bus Clock and Function register EBCF Initial value address: 0006F1...

  • Page 308

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Figure 12.2-2 External bus configuration registers External Area Configuration register 0 (lower byte) EACL0 Initial value address: 0006E0 00000000 External Area Configuration register 0 (upper byte) EACH0 Initial value address: 0006E1 XX000XXX External Area Configuration register 1 (lower byte) EACL1...

  • Page 309

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Figure 12.2-3 External bus configuration registers External Area Configuration register 4 (lower byte) EACL4 Initial value address: 0006E8 00000000 External Area Configuration register 4 (upper byte) EACH4 Initial value address: 0006E9 EASZ2 EASZ1 EASZ0 XX000110 External Area Configuration register 5 (lower byte)

  • Page 310

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.2.1 External Bus Mode registers (EBM) The External Bus Mode register defines the bus mode of the external bus interface. For the External Boot Vector fetch, the external bus mode byte is read externally from the address FFFFDF and written to the register directly after reading the Boot Vector.

  • Page 311

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Bit name Function bit [5:0] EAE[5:0]: • The EAE (External Area Enable) bits are used to activate the External address External area enable areas • ’0’ - the corresponding external address area is disabled. All other settings for this area have no effect.

  • Page 312

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.2.2 External Bus Clock and Function register (EBCF) The External Bus Clock and Function register controls the external bus clock, the External Ready and the Hold function: - Hold-function - External Ready function - Clock output enable - Clock active edge - Clock output mode...

  • Page 313

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE ■ External Bus Clock and Function register Figure 12.2-5 External Bus Clock and Function register (EBCF) Address: Initial value 0006F1 0 0 0 0 0 0 0 0 DIV2 DIV1 DIV0 R/W R/W R/W R/W R/W R/W R/W R/W...

  • Page 314

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Table 12.2-2 Function description of each bit of the External bus clock and Function register Bit name Function bit[10: 8] DIV[2:0]: • These bits control the clock divider for the external bus clock signal pin External bus clock (ECLK).

  • Page 315

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Table 12.2-2 Function description of each bit of the External bus clock and Function register Bit name Function bit 12 CKI: • This bit controls the active edge of the external bus clock. External bus clock •...

  • Page 316

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.2.3 External Bus Address output Enable registers (EBAE[2:0]) The External Bus Address output Enable registers controls the output function of each address line. ■ External Bus Address output Enable register Figure 12.2-6 External Bus Address output Enable register EBAE[2:0] Address: Initial value...

  • Page 317

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE All pins used for address outputs must be enabled by the corresponding bit of the EBAE register. This includes shared address/data pins in the multiplexed external bus mode. The address output of all address and address/data pins is active only during an external bus access. The address is not driven in a pause between two external bus accesses.

  • Page 318

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.2.4 External Bus Control Signal register (EBCS) This register is used to configure control signals of the external bus: - Activation of Write strobe, Read strobe and Byte select outputs - Activation of the Address strobe output and selection of the active level ■...

  • Page 319

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Bit name Function bit 8 LBE: • This bit enables the output of the LB byte select signal. Byte Select LB • ’0’ - output of the LB byte select signal is disabled (I/O port function enabled) output enable •...

  • Page 320

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.2.5 External Area Configuration registers (EACH/EACL[5:0]) The External Area Configuration registers are used to configure the following settings for each external area: - Automatic ready function - Address cycle length - Strobe signal timing - Write strobe function - Little/big endian data format...

  • Page 321

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Figure 12.2-8 External Area Configuration register (lower byte) EACL[5:0] Address: 0006E0 Initial value 0006E2 0006E4 0 0 0 0 0 0 0 0 0006E6 0006E8 0006EA R/W R/W R/W R/W R/W R/W R/W R/W bit2 bit1...

  • Page 322

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Bit name Function bit [2:0] R[2:0]: • These bits enable the automatic ready function and select the number of wait automatic ready cycles for the External area. function bit2 bit1 bit0 Automatic ready function Automatic ready function disabled...

  • Page 323

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Bit name Function bit 7 This bit selects the data width of the external bus for the corresponding address external bus data area. width • ’0’ - 16-bit data width selected. •...

  • Page 324

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Table 12.2-3 Endian selection access selected bus sequence on external bus width on width of the little endian (ES = ’0’) big endian (ES = ’1’) internal bus external bus 8-bit 16-bit internal...

  • Page 325

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Figure 12.2-9 External Area Configuration register (upper byte) EACH[5:0] Address: 0006E1 0006E3 Initial value 0006E5 X X 0 0 0 1 1 0 EASZ2 EASZ1 EASZ0 0006E7 0006E9 0006EB R/W R/W R/W R/W R/W R/W bit10 bit9...

  • Page 326

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Bit name Function bit[10:8] EASZ[2:0]: • These bits are used to define the size of the External area. The setting defines External Area Size which bits of the corresponding External Area Select register (EAS) are used for the address comparison.

  • Page 327

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE 12.2.6 External Area Select register (EAS[5:2]) The external bus interface supports two types of External address areas: - Areas with fixed address range (External areas 0 and 1) - Areas with selectable address range (External areas 2 to 5) ■...

  • Page 328

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 10.0000 in 4 sections. The external area 5 and the corresponding Chip select CS5 is used during external reset vector fetch, except on MB96(F)38x at external Boot Vector fetch in non-multiplexed bus mode, where external area 4 and CS4 are used.

  • Page 329

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE EAS2= 00 EACH2: EASZ = "110" - not decoded banks: 40...FF - decoded banks: 00...3F 00...0F: no access possible because not selectable for external area 2-5. 10...3F: access possible If an address inside the possible address range of the external bus is accessed but the address is not within the area of an activated external bus area, then the access has no effect (a read access returns ’0’...

  • Page 330: External Memory Access Control Signal Operation

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.3 External Memory Access Control Signal Operation This chapter describes the control signals during external bus operations. ■ Multiplexed external bus mode ● All timing charts are shown with following settings •...

  • Page 331

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE ● Timing charts for multiplexed bus modes Figure 12.3-1 Multiplexed 16-bit bus: Word and Byte access for EACL:STS=’0’ and EACL:ACE=’0’ ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area) A[23:16] Port function or other resource (address function not used in multiplexed external bus mode) A[15:00]...

  • Page 332

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Figure 12.3-2 Multiplexed 16-bit bus: Word and Byte access for EACL:STS=’1’ and EACL:ACE=’0’ ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area) A[23:16] Port function or other resource (address function not used in multiplexed external bus mode) A[15:00] Addr 1 Addr 2...

  • Page 333

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Figure 12.3-3 Multiplexed 16-bit bus: Word and Byte access for EACL:STS=’0’ and EACL:ACE=’1’ ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 A[23:16] Port function or other resource (address function not used in multiplexed external bus mode) A[15:00] Addr 1 Addr 2...

  • Page 334

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Figure 12.3-4 Multiplexed 16-bit bus: Word and Byte access for EACL:STS=’1’ and EACL:ACE=’1’ ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 A[23:16] Port function or other resource (address function not used in multiplexed external bus mode) A[15:00] Addr 1 Addr 2...

  • Page 335

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Figure 12.3-5 Multiplexed 8-bit bus: Word and Byte access for EACL:STS=’0’ and EACL:ACE=’0’ ECLK Addr 1 (CS1 area) Addr 1 + 1 Addr 2 (CS2 area) A[23:16] Port function or other resource (address function not used in multiplexed external bus mode) A[15:00] Addr 1 (CS1 area) Addr 1 + 1...

  • Page 336

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Figure 12.3-6 Multiplexed 16-bit bus: One automatic ready wait cycle added (EACL:R[2:0]=’001’, EACL:STS=’0’, EACL:ACE=’0)’ ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 A[23:16] Port function or other resource (address function not used in multiplexed external bus mode) A[15:00] Addr 1 Addr 2...

  • Page 337

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE ■ Non-multiplexed external bus mode ● All timing charts are shown with following settings • CSx active level is ’L’: EACHx:CSL=’0’ • all address outputs are enabled: EBAE:A[23:00]=’11...11’ • The inactive level of the external clock is ’0’: EBCF: CKI = ’0’ ●...

  • Page 338

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual ● Timing charts for non-multiplexed bus mode Figure 12.3-7 Non-multiplexed 16-bit bus: Word and Byte access for EACL:STS=’0’ ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area) Addr 4 (CS1 area) A[23:16] Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area)

  • Page 339

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Figure 12.3-8 Non-multiplexed 16-bit bus: Word and Byte access for EACL:STS=’1’ ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area) Addr 4 (CS1 area) A[23:16] Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area) Addr 4 (CS1 area) A[15:00] AD[15:08]...

  • Page 340

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Figure 12.3-9 Non-multiplexed 8-bit bus: Word and Byte access for EACL:STS=’0’ and EACL:ACE=’0’ ECLK Addr 1 (CS1 area) Addr 1 + 1 Addr 2 (CS2 area) Addr 3 (CS1 area) A[23:16] Addr 1 (CS1 area) Addr 1 + 1...

  • Page 341

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Figure 12.3-10 Non-multiplexed 16-bit bus: One automatic ready wait cycle added (EACL:R[2:0]=’001’, EACL:STS=’0’, EACL:ACE=’0)’ ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area) A[23:16] Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area) A[15:00]...

  • Page 342

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.3.1 Ready Function Enabling the external ready function (RDY-pin) and/or the automatic wait function enables access to low-speed memory and peripheral circuits. ■ Ready Function The read and write access to an external device can be extended with the ready function. The F MC-16FX MCU offers two possibilities to extend the data cycle of the external access, the automatic ready function and the external ready function.

  • Page 343

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Figure 12.3-11 Multiplexed 16-bit bus: Data cycle extended by external ready function ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) A[23:16] Port function or other resource (address function not used in multiplexed external bus mode) A[15:00] Addr 1 Addr 2...

  • Page 344

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Figure 12.3-12 Non-multiplexed 16-bit bus: Data cycle extended by automatic and external ready function ECLK Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area) A[23:16] Addr 1 (CS1 area) Addr 2 (CS1 area) Addr 3 (CS2 area) A[15:00]...

  • Page 345

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE 12.3.2 Hold Function The Hold function is used if multiple devices are used to access the same external bus. The Hold function is enabled by setting the HDE-bit in the External Bus Clock and Function register (EBCF) to ’1’.

  • Page 346

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual corresponding DDR register to "output" and writing the required pin level to the PDR register. The Hold state is left by setting the HRQ-pin back to ’0’. Then the HAK-pin outputs high-level, and all other output pins restore the values which they were driving before the Hold state.

  • Page 347

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Figure 12.3-13 Hold request in multiplexed 16-bit bus mode ECLK Addr 1 (CS1 area) Addr 2 (CS2 area) A[23:16] Addr 1 Addr 3 AD[15:08] Addr 1 Addr 3 AD[07:00] Addr 1 Write Data 1 Addr 3 AD[15:08]...

  • Page 348: Notes On Using The External Bus

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.4 Notes on using the external bus The handling of pins for the external bus is the same as for all other resources. This chapter describes how to set up the necessary pin to use the external bus interface. ■...

  • Page 349

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE Table 12.4-1 Recommended state of external bus pins Pin name Status Operation mode 8-bit 16-bit 8-bit 16-bit non-multiplexed non-multiplexed multiplexed multiplexed during external bus used for data used for data access used for address output (if enabled in EBAE0) AD[07:00]...

  • Page 350

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual Table 12.4-1 Recommended state of external bus pins Pin name Status Operation mode 8-bit 16-bit 8-bit 16-bit non-multiplexed non-multiplexed multiplexed multiplexed during external bus used for ALE/AS output (if enabled in EBCS:ASE) access ALE/AS pause between two...

  • Page 351

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE used for xxx output • The pin can be used as external bus output signal. (if enabled in Exxx) • The output of the external bus function can be enabled/disabled with the corresponding output enable bit in the Exxx register.

  • Page 352: External Boot Vector Fetch

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.5 External Boot Vector fetch Devices with external bus interface offer the possibility to read the Boot Vector (User program start address) via the external bus interface. This is possible in three different external bus operation modes depending on the MD[2:0] mode pin setting.

  • Page 353

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE ■ Procedure of External Boot Vector fetch 1. Internal reset is released. 2. MCU wakes up with RC clock and starts the Boot-ROM Start-up program. 3. Boot-ROM program reads the mode pin setting -> external vector mode detected. 4.

  • Page 354: Pin Status In Different Mcu States

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual 12.6 Pin status in different MCU states This chapter describes the status of the external bus pins in the following MCU states: - Reset - Run mode with external bus access - Run mode with internal access - Standby modes - Hold state...

  • Page 355

    MB96300 Super Series Hardware Manual CHAPTER 12 EXTERNAL BUS INTERFACE the Clock suspend mode is enabled and the ECLK clock divider is active, this is always the inactive level defined by EBCF:CKI.

  • Page 356

    CHAPTER 12 EXTERNAL BUS INTERFACE MB96300 Super Series Hardware Manual...

  • Page 357: I/o Ports

    CHAPTER 13 I/O PORTS This chapter explains the functions and operations of the I/O ports. 13.1 "I/O Ports" 13.2 "I/O Port Registers" 13.3 "Register usage"...

  • Page 358

    CHAPTER 13 I/O PORTS MB96300 Super Series Hardware Manual 13.1 I/O Ports Each pin of the ports can be specified as input or output using the direction register, if the corresponding peripheral does not use the pin. Before using a pin as input, it must be enabled by setting the Port Input Enable register.

  • Page 359: I/o Port Registers

    MB96300 Super Series Hardware Manual CHAPTER 13 I/O PORTS 13.2 I/O Port Registers Each general purpose port pin GPxx is controlled by nine types of registers. These are: • Port Data Register (PDR00 to PDRnn) • External Pin State Register (EPSR00 to EPSRnn) •...

  • Page 360

    CHAPTER 13 I/O PORTS MB96300 Super Series Hardware Manual 13.2.1 Port Data Register (PDRnn) Note that R/W for I/O ports differ from R/W for memory in the following points: • Input mode Read: The level at the corresponding pin is read. Write: Data is written to an output latch.

  • Page 361

    MB96300 Super Series Hardware Manual CHAPTER 13 I/O PORTS 1111.1111 (= output) PDR (= last value written to PDR) 0000.0000 0010.0000 (resource output enable) Resource output 0010.0000 current pin value 0010.0000 read by RMW instruction from PDR on 16LX 0010.0000 ->...

  • Page 362

    CHAPTER 13 I/O PORTS MB96300 Super Series Hardware Manual 13.2.2 External Pin State Register (EPSRnn) With this register the current state of the external pin can be read. ■ External Pin State Register Figure 13.2-3 External Pin State Registers EPSRnn Initial value Access Undefined...

  • Page 363

    MB96300 Super Series Hardware Manual CHAPTER 13 I/O PORTS 13.2.3 Data Direction Register (DDRnn) When a pin is used as a general purpose port, this register switches the corresponding pin to input mode or output mode. ■ Data direction register Figure 13.2-4 Data Direction Registers DDRnn Initial value...

  • Page 364

    CHAPTER 13 I/O PORTS MB96300 Super Series Hardware Manual 13.2.4 Port Input Enable Register (PIERnn) When a pin is used as general purpose port, the digital input is enabled or disabled with this register. When the digital input is disabled, no transverse current is drawn by the input stage at any input pin potential.

  • Page 365

    MB96300 Super Series Hardware Manual CHAPTER 13 I/O PORTS 13.2.5 Port Input Level Register (PILRnn) and Extended Port Input Level Register (EPILRnn) The digital input level of each pin can be programmed between CMOS Hysteresis, Automotive Hysteresis or TTL level with these two registers. ■...

  • Page 366

    CHAPTER 13 I/O PORTS MB96300 Super Series Hardware Manual Figure 13.2-7 Digital and analog Input CMOS 0307 Automotive Hysteresis PIER Digital Input CMOS 0208 PILR EPILR 2 Analog Input/ Output...

  • Page 367

    MB96300 Super Series Hardware Manual CHAPTER 13 I/O PORTS 13.2.6 Port Output Drive Register (PODRnn) The output drive option can be programmed with this register. Output drive strength is selectable between normal and reduced current. ■ Port Output Drive Register (PODRnn) Figure 13.2-8 Port Output Drive Register PODRnn Initial value...

  • Page 368

    CHAPTER 13 I/O PORTS MB96300 Super Series Hardware Manual 13.2.7 Port High Drive Register (PHDR) The high drive option can be enabled or disabled with this register. ■ Port High Drive Register Figure 13.2-9 Port High Drive Registers PHDRnn Initial value Access 00000000 R/W: Readable and writeable...

  • Page 369

    MB96300 Super Series Hardware Manual CHAPTER 13 I/O PORTS 13.2.8 Pull-Up Control Register (PUCR) The Pull-up resistor can be enabled or disabled with this register. ■ Pull-Up Control Register (PUCR) Figure 13.2-10 Pull-Up Control Register PUCRnn Initial value Access 00000000 R/W: Readable and writeable : Undefined Bits PUx (PUCR00 to PUCRnn)

  • Page 370: Register Usage

    CHAPTER 13 I/O PORTS MB96300 Super Series Hardware Manual 13.3 Register usage This chapter gives a summary about usage of IO registers. ■ Register settings for different port usage Table 13.3-1 Register settings for different port usage Register/ PIER EPSR PILR EPILR PUCR...

  • Page 371: Bit I/o Timer

    CHAPTER 14 16-BIT I/O TIMER This chapter explains the functions and operations of the 16-bit I/O Timer. 14.1 "Outline of 16-bit I/O Timer" 14.2 "16-Bit I/O Timer Registers" 14.3 "16-bit Free-Running Timer" 14.4 "Output Compare Unit" 14.5 "Input Capture Unit"...

  • Page 372: Outline Of 16-bit I/o Timer

    CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual 14.1 Outline of 16-bit I/O Timer The 16-bit I/O Timer consists of a 16-bit Free-Running Timer and Output Compare Units and Input Capture Units. It is used to generate pulse sequences and to measure the time duration between external events.

  • Page 373

    MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER ● The two input channels can operate independently. ● An interrupt can be issued upon a valid edge of an external input signal. The DMA can be activated upon an input capture interrupt. ■...

  • Page 374: Bit I/o Timer Registers

    CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual 14.2 16-Bit I/O Timer Registers The 16-bit I/O timer has the following registers: • 16-bit Free-Running Timer registers • 16-bit Output Compare registers • 16-bit Input Capture registers ■ 16-bit Free-Running Timer registers TCDTn Timer Data Register n TCCSHn...

  • Page 375

    MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER • etc. ■ 16-bit Input Capture registers IPCP(2n+0) Capture register 2n+0 IPCP(2n+1) Capture register 2n+1 Control Register (2n+0)/(2n+1) ICS(2n+0)/(2n+1) Capture Edge Register (2n+0)/(2n+1) ICE(2n+0)/(2n+1) Remark: The suffix "n" denotes the number of the Input Capture Unit (0, 1, 2, ...). The register name is composed by the register type name and the suffix.

  • Page 376: Bit Free-running Timer

    CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual 14.3 16-bit Free-Running Timer The 16-bit Free-Running Timer consists of a 16-bit up counter and a control status register. The count values of this timer are used as the base time for the Output Compare Units and Input Capture Units.

  • Page 377

    MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER 14.3.1 Data Register (TCDTn) The Data Register (TCDTn) can read the count value of the 16-bit Free-Running Timer. The counter value is cleared to "0000" upon a reset. The timer value can be set by writing a value to this register.

  • Page 378

    CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual 14.3.2 Control Status Register (TCCSLn) The control status register (TCCSLn) sets the operation mode of the 16-bit Free-Running Timer, starts and stops the 16-bit Free-Running Timer, and controls interrupts. ■ Control status register of Free-Running Timer (TCCSLn) Figure 14.3-3 Control status register of Free-Running Timer (TCCSLn) TCCSLn Initial value...

  • Page 379

    MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER Table 14.3-1 Control status register of Free-Running-Timer (TCCSLn) Bit name Function bit 7 • This bit is the interrupt request flag bit and clear bit • Writing "0": A possible interrupt is cleared. •...

  • Page 380

    CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual ■ Control status register of Free-Running Timer (TCCSHn) Figure 14.3-4 Control status register of Free-Running Timer (TCCSHn) TCCSHn ECKE FSEL Initial value 0 1 X X X X X X bit13-8 Undefined bit14...

  • Page 381

    MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER 14.3.3 16-bit Free-Running Timer Operation The 16-bit Free-Running Timer starts counting from counter value "0000" after the reset is released. The counter value is used as the base time for the 16-bit Output Compare and 16-bit Input Capture operations.

  • Page 382

    CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual ■ Clearing the counter at Compare Clear Register value match Figure 14.3-6 Clearing the Counter when the Compare Clear Register Value matches the 16-bit Free- Running Timer value Counter value FFFF BFFF 7FFF...

  • Page 383: Output Compare Unit

    MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER 14.4 Output Compare Unit The Output Compare Unit (OCU) consists of two 16-bit compare registers, two compare output pins, and one control register. If the value written to the compare register of this module matches the 16-bit free-running timer value, the output level of the pin can be toggled and an interrupt can be issued.

  • Page 384

    CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual 14.4.1 Output Compare Register (OCCP(2n) / OCCP(2n+1)) The 16-bit Output Compare registers are compared with the 16-bit Free-Running Timer. Since the initial register values are undefined, set appropriate value before enabling the operation.

  • Page 385

    MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER 14.4.2 Control Status Registers of Output Compare (OCS(2n) / OCS(2n+1)) The Control Status Register (OCS(2n) / OCS(2n+1)) sets the operation mode of output compare, starts and stops output compare, controls interrupts, and sets the external output pins.

  • Page 386

    CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual • for Output Compare Unit 0: n = 0, hence OCS0 has bits CST0, CST1, ICE0, ICE1, ICP0, ICP1 • for Output Compare Unit 1: n = 1, hence OCS2 has bits CST2, CST3, ICE2, ICE3, ICP2, ICP3 etc.

  • Page 387

    MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER Table 14.4-1 Output Compare Control Status Register (OCS(2n)) Bit name Function bit 7 ICP(2n+1) • These bits are used as compare match status flags. When the compare register value matches the 16-bit free-run timer value, the bit is set to "1". bit 6 ICP(2n+0) •...

  • Page 388

    CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual ■ Output Compare Control Status Register (OCS(2n+1)) Figure 14.4-4 Output Compare Control Status Register (OCS(2n+1)) OCS(2n+1) CMOD1 CMOD0 OTE Initial value 0 X X 0 0 0 0 0 R/W R/W R/W R/W bit 8 OTD(2n+0)

  • Page 389

    MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER Table 14.4-2 Output Compare Control Status Register (OCS(2n+1)) (2/2) Bit name Function bit 9 OTD(2n+1) These bits are used to change the pin output level when the Output Compare Unit output pin is enabled.

  • Page 390

    CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual Figure 14.4-5 Block diagram of output selection (OCU module 1) Compare Control 2 OUT2 CMOD1 CMP0EXT OUT3 CMOD0 Compare Control 3 For OCU module 1, which requires a match with Output Compare Register 0 if CMOD[1:0] = “10 ”...

  • Page 391

    MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER 14.4.3 16-bit Output Compare Operation In the 16-bit Output Compare operation, an interrupt request flag can be set and the output level can be toggled when the specified compare register value matches the 16-bit free-run timer value.

  • Page 392

    CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual OUT1 (3): The level is reversed by a match with compare register 0 (2) or with compare register 1 (3). For OUT4, OUT5, OUT6 and OUT7, compare register 4 plays the same role as compare register 0 above. Figure 14.4-7 Sample of a output waveform when CMOD[1:0] = "01 "...

  • Page 393

    MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER Figure 14.4-8 Output waveform when OCS1:CMOD[1:0] = "01 " and OCS3:CMOD[1:0] = "10 " Counter value FFFF BFFF 7FFF 3FFF 0000 Time Reset OCCP0 value BFFF OCCP1 value 7FFF OCCP2 value 3FFF OCCP3 value 5FFF...

  • Page 394

    CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual Figure 14.4-9 Output waveform when OCS1:CMOD[1:0] = "11 " and OCS3:CMOD[1:0] = "11 " Counter value FFFF BFFF 7FFF 3FFF 0000 Time Reset OCCP0 value BFFF OCCP1 value 7FFF OCCP2 value 3FFF OCCP3 value 5FFF...

  • Page 395

    MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER ■ Output compare timing In output compare operation, a compare match signal is generated when the Free-Running Timer value matches the specified compare register value. The output value can be reversed and an interrupt can be issued.

  • Page 396: Input Capture Unit

    CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual 14.5 Input Capture Unit The Input Capture Unit (ICU) detects a rising or falling edge or both edges of an external input signal and stores a 16-bit Free-Running Timer value at that time in a register. In addition, the Input Capture Unit can generate an interrupt upon detection of an edge.

  • Page 397

    MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER 14.5.1 Input Capture Unit Register Details The Input Capture Unit is configured by the Control Status Register (ICS(2n)(2n+1)) and the Edge Register (ICE(2n)(2n+1)). The Input Capture Unit has a 16bit data register (IPCPn). This register stores a value from the 16-bit Free-Running Timer when a valid edge of the corresponding external pin input waveform is detected.

  • Page 398

    CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual ■ Input Capture Control Status Register (ICS(2n)(2n+1)) Figure 14.5-3 Input Capture Control Status Register (ICS(2n)(2n+1)) ICS(2n)(2n+1) initial value 0 0 0 0 0 0 0 0 ICE ICE EG R/W R/W R/W R/W R/W R/W R/W bit1 bit0...

  • Page 399

    MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER Table 14.5-2 Input Capture Unit Control Status Register bits Bit name Function bit7 ICP(2n+1): • This bit is used as interrupt request flag for Input Capture Unit n, second Interrupt request flag channel.

  • Page 400

    CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual Figure 14.5-4 Input Capture Unit Edge Register (ICE(2n)(2n+1)) ICE(2n)(2n+1) Initial value RES IEI(2n+1)IEI(2n) X X X X X X 0 0 R/W R/W bit8 IEI(2n) Input capture valid edge indication bit for ICU0 falling edge detected rising edge detected bit9...

  • Page 401

    MB96300 Super Series Hardware Manual CHAPTER 14 16-BIT I/O TIMER 14.5.2 16-bit Input Capture Operation In 16-bit Input Capture operation, an interrupt can be generated upon detection of the specified edge, fetching the 16-bit Free-Running Timer value and writing it to the capture data register.

  • Page 402

    CHAPTER 14 16-BIT I/O TIMER MB96300 Super Series Hardware Manual Figure 14.5-5 Example of Input Capture fetch timing Counter value FFFF BFFF 7FFF 3FFF 0000 Time Reset IN example Capture 0 Undefined 3FFF Capture 1 Undefined 7FFF Capture example Undefined BFFF 3FFF Capture 0...

  • Page 403: Bit Reload Timer (with Event Count Function)

    CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) This chapter explains the functions and operations of the 16-bit Reload Timer (with the Event Count Function). 15.1 "Outline of 16-Bit Reload Timer (with Event Count Function)" 15.2 "16-Bit Reload Timer (with Event Count Function)" 15.3 "Internal Clock and External Event Counter Operations of 16-bit Reload Timer"...

  • Page 404: Outline Of 16-bit Reload Timer (with Event Count Function)

    CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) MB96300 Super Series Hardware 15.1 Outline of 16-Bit Reload Timer (with Event Count Function) The 16-bit reload timer consists of a 16-bit down-counter, a 16-bit reload register, one input pin (TINn) and one output pin (TOTn), and control registers. ■...

  • Page 405

    MB96300 Super Series Hardware Manual CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT Figure 15.1-1 Block diagram of 16-bit reload timer 16-bit reload register TMISR Reload RELD 16-bit down-counter OUTE detection OUTL GATE INTE CTL. FSEL CSL1 Clock selector CNTE CSL0 Re-trigger Port (TINn)

  • Page 406

    CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) MB96300 Super Series Hardware 15.2 16-Bit Reload Timer (with Event Count Function) The 16-bit Reload Timer has the following registers: • Timer Control Status Register (TMCSRn) • 16-bit Timer Register (TMRn) / 16-bit Reload Register (TMRLRn) ■...

  • Page 407

    MB96300 Super Series Hardware Manual CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT 15.2.1 Timer Control Status Register (TMCSRn) The Timer Control Status Register controls the operation mode and interrupts for the 16- bit Reload Timer. ■ Register layout of Timer Control Status Register (TMCSRn) Figure 15.2-2 Register layout of Timer Control Status Register (TMCSRn) TMCSRHn FSEL...

  • Page 408

    CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) MB96300 Super Series Hardware Table 15.2-1 Clock sources for CSL0/1 and FSEL bit settings (Continued) FSEL CSL1 CSL0 Clock Source (Time for peripheral clock CLKP1 = 24 MHz) External event count mode External event count mode / 2 [Bits 9, 8, 7] MOD2, MOD1, MOD0 (Operation mode and TINn function) These bits set the operation mode and input pin (TINn) functions.

  • Page 409

    MB96300 Super Series Hardware Manual CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT [Bit 6] OUTE (Output enable) If this bit is set to "1", the pin TOTn is used as Reload Timer output. If this bit is set to "0" the timer output TOTn is disabled.

  • Page 410

    CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) MB96300 Super Series Hardware 15.2.2 Register Layout of 16-bit Timer Register (TMRn)/16-bit Reload Register (TMRLRn) • TMRn contents Reading this register returns the count value of the 16-bit Reload Timer. The initial value is undefined.

  • Page 411: Internal Clock And External Event Counter Operations Of 16-bit Reload Timer

    MB96300 Super Series Hardware Manual CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT 15.3 Internal Clock and External Event Counter Operations of 16- bit Reload Timer In internal clock mode, the peripheral clock CLKP1 with different divider settings can be selected as the clock source for operating the Reload Timer.

  • Page 412

    CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) MB96300 Super Series Hardware Figure 15.3-2 Trigger input operation of 16-bit Reload Timer Count clock Rising edge detected Prescaler clear Counter Reload data XXXX Load 2.5T When used as a gate input, the counter only counts while the active level specified by the MOD0 bit of the control register is input to the TINn pin.

  • Page 413: Underflow Operation Of 16-bit Reload Timer

    MB96300 Super Series Hardware Manual CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT 15.4 Underflow Operation of 16-bit Reload Timer An underflow is defined for this timer as the time when the counter value changes from 0000 to FFFF . Therefore, an underflow occurs after (reload register setting + 1) counts. ■...

  • Page 414: Output Pin Functions Of 16-bit Reload Timer

    CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) MB96300 Super Series Hardware 15.5 Output Pin Functions of 16-bit Reload Timer In reload mode, the TOTn pin performs toggle output (inverts at each underflow). In one- shot mode, the TOTn pin is used as a pulse output that shows the configured level while the counting is in progress.

  • Page 415: Counter Operation State

    MB96300 Super Series Hardware Manual CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT 15.6 Counter Operation State The counter state is determined by the CNTE bit in the control status register and the internal WAIT signal. Available states are: CNTE = "0" and WAIT = "1" (STOP state), CNTE = "1"...

  • Page 416: Cascading Of 16-bit Reload Timers

    CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) MB96300 Super Series Hardware 15.7 Cascading of 16-bit Reload Timers The cascading of multiple adjacent 16-bit Reload Timers allows the user to create its own n * 16-bit-Reload Timer (Example: 3 adjacent Reload Timers available on device). ■...

  • Page 417

    MB96300 Super Series Hardware Manual CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT ■ Reload Timer Input Select Register (TMISR) Reload Timer Input Select Register (TMISR) Figure 15.7-2 TMISR TMS5 TMS4 TMS3 TMS2 TMS1 TMS0 Initial value X X 0 0 0 0 0 0 bit0 TMIS0 Reload Timer 0 Input Select...

  • Page 418

    CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION) MB96300 Super Series Hardware...

  • Page 419: Programmable Pulse Generator

    CHAPTER 16 PROGRAMMABLE PULSE GENERATOR This chapter explains the functions and operations of the Programmable Pulse Generator. 16.1 "Outline of Programmable Pulse Generator" 16.2 "Registers" 16.3 "Operation of Programmable Pulse Generator" 16.4 "Cautions"...

  • Page 420: Outline Of Programmable Pulse Generator

    CHAPTER 16 PROGRAMMABLE PULSE GENERATOR MB96300 Super Series Hardware Manual 16.1 Outline of Programmable Pulse Generator Programmable Pulse Generators (PPGs) are used to obtain one-shot (rectangular wave) output or pulse width modulation (PWM) output. With their software-programmable cycle and duty capability, the PPGs comfortably fit into a broad range of applications. ■...

  • Page 421

    MB96300 Super Series Hardware Manual CHAPTER 16 PROGRAMMABLE PULSE GENERATOR Activation trigger: • Software trigger • Internal trigger • External trigger (TTG pins) Freely configurable Reload Timer as additional prescalar input ■ Simplified block diagram of Programmable Pulse Generator Figure 16.1-1 Simplified block diagram of Programmable Pulse Generator Period value Reload Borrow...

  • Page 422

    CHAPTER 16 PROGRAMMABLE PULSE GENERATOR MB96300 Super Series Hardware Manual Figure 16.1-2 Configuration diagram of Programmable Pulse Generator Period value Duty value MDSE PCNn: bit 13 PWM operation PCSR PDUT One shot PGMS OSEL PCNn: bit 9, bit 0 Reload Reload Normal output Inverted output...

  • Page 423: Registers

    MB96300 Super Series Hardware Manual CHAPTER 16 PROGRAMMABLE PULSE GENERATOR 16.2 Registers The programmable pulse generator has the following registers: • PPG Control Status register (PCNn) • General Control register 1 (GCN1g), one per group of 4 PPGs • General Control register 2 (GCN2g), one per group of 4 PPGs •...

  • Page 424

    CHAPTER 16 PROGRAMMABLE PULSE GENERATOR MB96300 Super Series Hardware Manual Figure 16.2-2 PPG Control Status register (PCNn) PCNHn CNTE STGR MDSE RTRG CKS1 CKS0 PGMS Access: R0/W R/W R/W R/W Rx/Wx Initial value: Rewrite during operation: PCNLn EGS1 EGS0 IREN IRQF IRS1 IRS0...

  • Page 425

    MB96300 Super Series Hardware Manual CHAPTER 16 PROGRAMMABLE PULSE GENERATOR Bits 11-10: Counter clock selection CKS1 CKS0 Down Counter Count Clock Selection Clock selected by CKSEL Clock selected by CKSEL divided by 4 Clock selected by CKSEL divided by 16 Clock selected by CKSEL divided by 64 Bit 9: PPG output mask selection PGMS...

  • Page 426

    CHAPTER 16 PROGRAMMABLE PULSE GENERATOR MB96300 Super Series Hardware Manual Counter borrow or the counter equals the duty value. Select the operation in which to generate an interrupt request. Bit 1: PPG output enable Operation Output disabled Output enabled Bit 0: PPG output polarity specification OSEL Operation Normal polarity...

  • Page 427

    MB96300 Super Series Hardware Manual CHAPTER 16 PROGRAMMABLE PULSE GENERATOR PPG0 to PPGn as selected are activated when the edge specified by the Trigger Input Edge Selection bits (PCNn:EGS[1:0]) are detected by the specified activation trigger. ■ General Control Register 2 (GCN2g) The General Control Register 2 (GCN2x) generates internal trigger levels using software for a PPG block of 4 PPGs.

  • Page 428

    CHAPTER 16 PROGRAMMABLE PULSE GENERATOR MB96300 Super Series Hardware Manual Figure 16.2-5 PPG Cycle Setting Register (PCSRn) PCSRHn Access: Initial value: PCSRLn Access: Initial value: W : Write only x : undefined The PPG Period Setting registers come with buffers. Transfers from the buffers to the counter take place automatically upon counter borrow.

  • Page 429

    MB96300 Super Series Hardware Manual CHAPTER 16 PROGRAMMABLE PULSE GENERATOR Figure 16.2-7 PPG Timer Register (PTMRn) PTMRHn Access: Initial value: PTMRLn Access: Initial value: : Read only, write has no effect x : undefined The count of the 16-bit down counter can be read.

  • Page 430: Operation Of Programmable Pulse Generator

    CHAPTER 16 PROGRAMMABLE PULSE GENERATOR MB96300 Super Series Hardware Manual 16.3 Operation of Programmable Pulse Generator The Programmable Pulse generators (PPGs) provide programmable pulse output independently or jointly. The individual modes of operation are described below ■ PWM Operation In PWM operation, variable-duty pulses are generated from the PPG pin. Enable count CNTE Activation trigger...

  • Page 431

    MB96300 Super Series Hardware Manual CHAPTER 16 PROGRAMMABLE PULSE GENERATOR • (11) Counter borrow. • (12) Clear the PPG pin output level (return to normal). • (13) Reload the cycle value. • (14) Reload the duty value. • (15) Steps from (7) to (14) are iterated. •...

  • Page 432

    CHAPTER 16 PROGRAMMABLE PULSE GENERATOR MB96300 Super Series Hardware Manual • (6) Counter down count. • (7) The down counter equals the duty value. • (8) Inverses the PPG pin output level. • (9) Counter down count. • (10) Counter borrow. •...

  • Page 433: Cautions

    MB96300 Super Series Hardware Manual CHAPTER 16 PROGRAMMABLE PULSE GENERATOR 16.4 Cautions This section describes the cautions to be considered while using the programmable pulse generator ■ Cautions • If the Interrupt Request flag (PCN:IRQF) equals “1” and the Interrupt Request flag is set to “0” at the same timing, the setting of the Interrupt Request flag to “1”...

  • Page 434

    CHAPTER 16 PROGRAMMABLE PULSE GENERATOR MB96300 Super Series Hardware Manual PPG stops with its status (count and output level) being latched. If the Timer Operation Enable bit (PCN:CNTE) is subsequently set to “1” to enable the PPG, it restarts from the point of interruption.

  • Page 435: External Interrupts

    CHAPTER 17 EXTERNAL INTERRUPTS This chapter explains the functions and operations of the External Interrupts. 17.1 "Outline of External Interrupts" 17.2 "External Interrupt Registers" 17.3 "Notes on using the External Interrupt functions"...

  • Page 436: Outline Of External Interrupts

    CHAPTER 17 EXTERNAL INTERRUPTS MB96300 Super Series Hardware Manual 17.1 Outline of External Interrupts The External Interrupt detects a signal input to an external interrupt pin and generates an interrupt request. ■ External interrupts For an external interrupt request, four request levels are available: "H", "L", rising edge, and falling edge are available.

  • Page 437

    MB96300 Super Series Hardware Manual CHAPTER 17 EXTERNAL INTERRUPTS ■ External interrupts registers Initial value ENIR0 00000000 ENIR1 EN15 EN14 EN13 EN12 EN11 EN10 00000000 EIRR0 00000000 EIRR1 ER15 ER14 ER13 ER12 ER11 ER10 00000000 ELVR0 00000000 ELVR0 00000000 ELVR1 00000000 LB11 LA11...

  • Page 438: External Interrupt Registers

    CHAPTER 17 EXTERNAL INTERRUPTS MB96300 Super Series Hardware Manual 17.2 External Interrupt Registers The External Interrupt mdule has the following registers: • Interrupt Enable register (ENIRn: External Interrupt Request Enable Register) • Interrupt flag (EIRRn: External Interrupt Request Register) • Request level setting register (ELVRn: External Level Register) ■...

  • Page 439

    MB96300 Super Series Hardware Manual CHAPTER 17 EXTERNAL INTERRUPTS Note: When clearing the interrupt flag, make sure to clear the flag which caused the interrupt alone but not others. ■ Request level setting register (ELVRn: External Interrupt Level Register) Figure 17.2-3 External Interrupt Level Register (ELVRn) ELVR0 Initial value 00000000...

  • Page 440: Notes On Using The External Interrupt Functions

    CHAPTER 17 EXTERNAL INTERRUPTS MB96300 Super Series Hardware Manual 17.3 Notes on using the External Interrupt functions The following points must be considered to use the External Interrupt function. • Conditions on the behavior of external circuit for use of DMA •...

  • Page 441: A/d Converter

    CHAPTER 18 A/D CONVERTER This chapter explains the function and operation of the A/ D converter. 18.1 "Outline of A/D Converter" 18.2 "Registers for A/D Converter" 18.3 "Operation of A/D Converter" 18.4 "Conversion using DMA" 18.5 "Conversion Data Protection Function"...

  • Page 442: Outline Of A/d Converter

    CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual 18.1 Outline of A/D Converter The A/D converter converts analog input voltages to digital values. ■ Outline of A/D converter • Conversion time: 1.9 µs min. per channel (with 24-MHz machine clock) •...

  • Page 443

    MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER ■ Block diagram of A/D converter Figure 18.1-1 Block diagram of A/D converter ADSEL AVcc RH/L AVss D/A Converter AN32 Sequential comparison register AN31 Comparator Sample & Hold circuits ADCR Data Register Hold circuit Setting register L Setting register H...

  • Page 444: Registers For A/d Converter

    CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual 18.2 Registers for A/D Converter The A/D converter has the following registers: • Control status register: ADCS • Data register: ADCR • Setting register: ADSR • Extended configuration register: ADECR • Analog input enable register: ADERx...

  • Page 445

    MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER ■ Registers for A/D converter Figure 18.2-1 Registers of the A/D Converter A/D control status register ( Upper) Bit No. BUSY INTE PAUS STS1 STS0 STRT ADCSH Read/write (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

  • Page 446

    CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual 18.2.1 Control status register (ADCS) The control status register (ADCS) controls the A/D converter and indicates its status. Do not rewrite ADCS during A/D conversion. ■ Control Status Register (ADCS) Figure 18.2-2 A/D control status register (ADCS) A/D control status register (Upper) Bit No.

  • Page 447

    MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER [bit 14] INT (interrupt) This bit is set when converted data is written to ADCR. When this bit is set with bit5 (INTE) set to “1”, an interrupt request is generated. If DMA is configured and enabled, DMA is activated instead. Writing “1”...

  • Page 448

    CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual In a mode allowing two or more activation causes, A/D conversion is activated by the source that occurs first. When changing the setting of these bits during A/D conversion, the result is immediately reflected. Therefore it is not a recommended practice.

  • Page 449

    MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER Note: • The A/D conversion in the continuous or stop mode continues until it is stopped by the BUSY bit. • Write 0 to the BUSY bit to stop the A/D conversion. •...

  • Page 450

    CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual 18.2.2 Data Register (ADCR) The data register (ADCR) is used to store digital value generated as a result of conversion. The register value is rewritten every time the conversion ends. Normally, the last converted value is stored in these register's bits.

  • Page 451

    MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER 18.2.3 Setting Register (ADSR) The setting register (ADSR) is used to set the A/D conversion time and the sampling channels and to indicate the current sampling channel. ■ Setting Register (ADSR) Figure 18.2-4 Setting register (ADSR) A/D setting register (Upper) Bit No.

  • Page 452

    CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual 1.2µs; For 3.0V Avcc < 4.5V If the driving impedance, R is greater than 1.5 kΩ, the sampling time must be greater than T given by samp the following formula; = (2.25 kΩ + Rext) × 10.7pF × 7; For 4.5V Avcc 5.5V samp...

  • Page 453

    MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER Table 18.2-5 Starting Channel Settings (Continued) (2/2) ANS4 ANS3 ANS2 ANS1 ANS0 Starting channel when Starting channel when ADECR:ADSEL = 0 ADECR:ADSEL = 1 AN29* AN61* AN30* AN62* AN31* AN63* * For the highest ADC channel number available on the device, please refer to the corresponding data sheet.

  • Page 454

    CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual Note: • When writing to this register, always use word access. When byte write or read-modify-write is performed for this register, A/D conversion may be started from an unintended channel. • When the same channel is written to the ANE4 to ANE0 bits and to the ANS4 to ANS0 bits, conversion is performed for only 1 channel (single channel conversion).

  • Page 455

    MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER 18.2.4 Extended Configuration Register (ADECR) The extended configuration register (ADECR) is used to enable the A/D Converter input channels 32 and higher. It also enables to switch the A/D converters high and low reference voltage between AVRH + AVRL, AVRH + AVSS and AVRH2 + AVSS.

  • Page 456

    CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual Figure 18.2-6 Switching of ADC Reference Voltage (LSEL="0", HSEL="0"). AVCC AVCC AVRH High reference voltage ADECR LSEL=0 HSEL=0 AVRL/AVRH2 Low reference voltage AVSS AVSS Note: This setting is compatible to16LX configuration of A/D converter. It enables to have the low reference voltage of the A/D converter different from AVSS potential.

  • Page 457

    MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER Figure 18.2-7 Switching of ADC Reference Voltage (LSEL="0", HSEL="1" or LSEL="1", HSEL="0") AVCC AVCC AVRH High reference voltage ADECR LSEL=0 HSEL=1 LSEL=1 HSEL=0 AVRL/AVRH2 Low reference voltage AVSS AVSS Note: This setting can be used in the case the low reference voltage of the A/D converter is equal to AVSS potential (e.g.

  • Page 458

    CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual Figure 18.2-8 Switching of ADC Reference Voltage (LSEL="1", HSEL="1" AVCC AVCC AVRH High reference voltage ADECR LSEL=1 HSEL=1 AVRL/AVRH2 Low reference voltage AVSS AVSS Note: This setting can be used in the case the low reference voltage of the A/D converter is equal to AVSS potential (e.g.

  • Page 459

    MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER 18.2.5 Analog Input Enable Register (ADERx) This register enables the analog input functions for the AD converter ■ Analog input enable register (ADERx) Figure 18.2-9 Analog input enable register (ADERx) ADER0 Bit No.

  • Page 460: Operation Of A/d Converter

    CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual 18.3 Operation of A/D Converter The A/D converter operates using the sequential-comparison converter system; and 10 bits or 8 bits can be selected for the A/D converter's resolution. Since this A/D converter has only one register (10 bits; conversion result data register ADCR) for storing conversion results, this register is rewritten every time conversion is ended.

  • Page 461: Conversion Using Dma

    MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER 18.4 Conversion using DMA Figure 18.4-1 gives an example of flow for the activation of A/D conversion to the transfer of converted data in continous mode. ■ Conversion using DMA Figure 18.4-1 Example of flow for the activation of A/D conversion to the transfer of converted data in continous mode.

  • Page 462: Conversion Data Protection Function

    CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual 18.5 Conversion Data Protection Function The A/D converter has the converted-data protection function, is featured by continuous conversion and securing two or more data using DMA. Only one conversion data register (ADCR) is provided, so when A/D conversion is continuously performed, converted data is stored every time one conversion is ended, destroying the previous data.

  • Page 463

    MB96300 Super Series Hardware Manual CHAPTER 18 A/D CONVERTER ■ Example of flow of Conversion Data Protection Function (when DMA is used) Figure 18.5-1 Example of flow of Conversion Data Protection Function (when DMA is used) Set DMA Start continuous A/D conversion First conversion end Store in data register Second conversion end...

  • Page 464

    CHAPTER 18 A/D CONVERTER MB96300 Super Series Hardware Manual...

  • Page 465: Alarm Comparator

    CHAPTER 19 ALARM COMPARATOR This chapter explains the functions and operations of the Alarm Comparator. 19.1 "Outline of Alarm Comparator" 19.2 "Alarm Comparator Registers" 19.3 "Alarm Comparator operating modes"...

  • Page 466: Outline Of Alarm Comparator

    CHAPTER 19 ALARM COMPARATOR MB96300 Super Series Hardware Manual 19.1 Outline of Alarm Comparator This chapter provides an overview of the Alarm Comparator (also called Under/Overflow voltage Detection), describes the register structure, modes and the operation of the Alarm Comparator ■...

  • Page 467

    MB96300 Super Series Hardware Manual CHAPTER 19 ALARM COMPARATOR ■ Block diagram of Alarm Comparator Figure 19.1-1 Block diagram of Alarm Comparator Analog part Digital part AVCC Interrupt logic ALARMn OUT1 OUT2 VREF INTREF AVSS CLKP1 Note: • The suffix ’n’ denotes the number of the Alarm Comparator module.

  • Page 468: Alarm Comparator Registers

    CHAPTER 19 ALARM COMPARATOR MB96300 Super Series Hardware Manual 19.2 Alarm Comparator Registers The Alarm Comparator has the following two registers: • Alarm Comparator Control/Status register (ACSRn) • Alarm Comparator Extended Control/Status register (AECSRn) ■ Alarm Comparator Control/Status register (ACSRn) Figure 19.2-1 Structure of Alarm Comparator control/status register Bits ACSRn...

  • Page 469

    MB96300 Super Series Hardware Manual CHAPTER 19 ALARM COMPARATOR Analog input voltage < V when AECSRn:INTREF = 0 or EVTL analog input voltage < V when AECSRn:INTREF = 1 IVTL Analog input voltage > V when AECSRn:INTREF = 0 or EVTL analog input voltage >...

  • Page 470

    CHAPTER 19 ALARM COMPARATOR MB96300 Super Series Hardware Manual ■ Alarm Comparator Extended Control/Status Register (AECSRn) Figure 19.2-2 Structure of Alarm Comparator Extended Control/Status register AECSRn Initial value INTREF X X X X X 0 X 0 bit8 INTREF Internal reference voltage select bit Reference voltage derived from AVCC/AVSS Reference voltage derived from internal reference VREF bit9...

  • Page 471: Alarm Comparator Operating Modes

    MB96300 Super Series Hardware Manual CHAPTER 19 ALARM COMPARATOR 19.3 Alarm Comparator operating modes The Alarm Comparator circuit can operate in interrupt or polling mode. The internal interrupt logic will detect each interrupt event independent of setting of the IEN bit. ■...

  • Page 472

    CHAPTER 19 ALARM COMPARATOR MB96300 Super Series Hardware Manual Table 19.3-2 Alarm Comparator operation modes STOP TIMER SLEEP Digital part ACSR:PD Analog part operating run mode operating power down stopped stopped Precaution: The outputs of the Alarm Comparator (analog parts) will remain undefined for at least 3 us after power on and also after reentering the run mode.

  • Page 473: Usart

    CHAPTER 20 USART This chapter explains the functions and operation of the LIN USART. 20.1 "Overview of USART" 20.2 "Configuration of USART" 20.3 "USART Pins" 20.4 "USART Registers" 20.5 "USART Interrupts" 20.6 "USART Baud Rates" 20.7 "Operation of USART" 20.8 "Notes on Using USART"...

  • Page 474: Overview Of Usart

    CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.1 Overview of USART The USART with LIN (Local Interconnect Network) - Function is a general-purpose serial data communication interface for performing synchronous or asynchronous communication with external devices. The USART provides bidirectional communication function (normal mode), master-slave communication function (multiprocessor mode in master/slave systems), and special features for LIN-bus systems (working both as master or as slave device).

  • Page 475

    MB96300 Super Series Hardware Manual CHAPTER 20 USART Table 20.1-1 USART functions (2/2) Item Function Synchronous mode Function as Master- or Slave-USART Transceiving pins Direct access possible LIN bus options • Operation as master device • Operation as slave device •...

  • Page 476

    CHAPTER 20 USART MB96300 Super Series Hardware Manual shown in the following table: Table 20.1-3 Mode bit setting Mode Description Asynchronous (normal mode) Asynchronous (multiprocessor mode) Synchronous (normal mode) Asynchronous (LIN mode)

  • Page 477: Configuration Of Usart

    MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.2 Configuration of USART This section provides a short overview on the building blocks of USART. ■ Block diagram of USART USART consists of the following blocks: • Reload Counter • Reception Control Circuit •...

  • Page 478

    CHAPTER 20 USART MB96300 Super Series Hardware Manual Figure 20.2-1 Block diagram of USART AICD PE ORE FRE (OTO, EXT, Peripheral clock REST) transmission clock LBIE Reload Interrupt reception clock Counter Generation TRANSMISSION SCKn circuit CONTROL RECEPTION CIRCUIT CONTROL CIRCUIT Start bit Transmission Detection...

  • Page 479

    MB96300 Super Series Hardware Manual CHAPTER 20 USART bit detection circuit detects start bits from the serial input signal and sends a signal to the reload counter to synchronize it to the falling edge of these start bits. The reception parity counter calculates the parity of the reception data.

  • Page 480

    CHAPTER 20 USART MB96300 Super Series Hardware Manual ● LIN Synch Break Generation Circuit The LIN break generation circuit generates a LIN break of a determined length. ● Bus Idle Detection circuit The bus idle detection circuit recognizes if neither reception nor transmission is going on. In this case, the circuit generates the special flag bits TBI and RBI.

  • Page 481

    MB96300 Super Series Hardware Manual CHAPTER 20 USART • Directly accessing SINn and SOTn pins • Specifying continuous clock output operation • Specifying sampling clock edge ● Extended Communication Control Register (ECCRn) This register performs the following functions: • Indicating bus idle state •...

  • Page 482: Usart Pins

    CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.3 USART Pins This section describes the USART pins and provides a pin block diagram. ■ USART pins The USART pins are shared with general purpose ports. Table 20.3-1 "USART pins" lists the pin functions, I/O formats, and settings required to use the USART.

  • Page 483: Usart Registers

    MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.4 USART Registers The following figure shows the USART registers. ■ USART registers Figure 20.4-1 USART registers USART registers bit15 bit8 bit7 bit0 SCRn (Serial Control Register) SMRn (Serial Mode Register) SSRn (Serial Status Register) RDRn/TDRx (RX, TX Data Register) ESCRn (Extended Status/Control Reg.) ECCRn (Extended Comm.

  • Page 484

    CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.4.1 Serial Control Register (SCRn) This register specifies parity bits, selects the stop bit and data lengths, selects a frame data format in mode 1, clears the reception error flag, and specifies whether to enable transmission and reception.

  • Page 485

    MB96300 Super Series Hardware Manual CHAPTER 20 USART ■ Serial control register (SCRn) Figure 20.4-2 Configuration of the serial control register (SCRn) SCRn Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W bit8 Transmission enable Disable Transmission Enable Transmission...

  • Page 486

    CHAPTER 20 USART MB96300 Super Series Hardware Manual Table 20.4-1 Functions of each bit of control register (SCRn) Bit name Function bit14 When parity is provided and enabled this bit selects even (0) or odd (1) parity. Parity selection bit bit13 SBL: This bit selects the length of the stop bit of an asynchronous data frame or a...

  • Page 487

    MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.4.2 Serial mode register (SMRn) This register selects an operation mode and baud rate clock and specifies whether to enable output of serial data and clocks to the corresponding pin.

  • Page 488

    CHAPTER 20 USART MB96300 Super Series Hardware Manual ■ Serial mode register (SMRn) Figure 20.4-3 Configuration of the serial mode register (SMRn) SMRn Initial value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W bit0 Serial data output enable bit of LIN-USART LIN-UART serial data output pin disabled LIN-UART serial data output pin enabled...

  • Page 489

    MB96300 Super Series Hardware Manual CHAPTER 20 USART Table 20.4-2 Bit function of the serial mode register (SMRn) Bit name Function bit5 OTO: This bit sets an external clock directly to the LIN-USART’s serial clock. This function One-to-one external is used for operating mode 2 (synchronous) slave mode operation. clock selection bit bit4 EXT:...

  • Page 490

    CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.4.3 Serial Status Register (SSRn) This register checks the transmission and reception status and error status, it also enables and disables the transmission and receive interrupts.

  • Page 491

    MB96300 Super Series Hardware Manual CHAPTER 20 USART ■ Serial status register (SSRn) Figure 20.4-4 Configuration of the serial status register (SSRn) SSRn Initial value 0 0 0 0 1 0 0 0 R/W R/W bit8 Transmission Interrupt enable Disables Transmission Interrupt Enables Transmission Interrupt bit9 Reception Interrupt enable...

  • Page 492

    CHAPTER 20 USART MB96300 Super Series Hardware Manual Table 20.4-3 Functions of each bit of status register (SSRn) Bit name Function bit14 ORE: • This bit is set to 1 when an overrun error occurs during reception. Overrun error flag bit •...

  • Page 493

    MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.4.4 Reception and Transmission Data Register (RDRn/TDRn) The reception data register (RDRn) holds the received data. The transmission data register (TDRn) holds the transmission data. Both RDRn and TDRn registers are located at the same address.

  • Page 494

    CHAPTER 20 USART MB96300 Super Series Hardware Manual ● Transmission: When data to be transmitted is written to the transmission data register in transmission enable state, it is transferred to the transmission shift register, then converted to serial data, and transmitted from the serial data output terminal (SOTn pin).

  • Page 495

    MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.4.5 Extended Status/Control Register (ESCRn) This register provides several LIN functions, direct access to the SINn and SOTn pin and setting for USART synchronous clock mode.

  • Page 496

    CHAPTER 20 USART MB96300 Super Series Hardware Manual ■ Extended status/control register (ESCRn) Figure 20.4-6 Configuration of the extended status/control register (ESCRn) ESCRn Initial value 0 0 0 0 0 1 0 0 R/W R/W R/W R/W R/W R/W bit8 SCES Sampling Clock Edge Selection (Mode 2) Sampling on rising clock edge (normal)

  • Page 497

    MB96300 Super Series Hardware Manual CHAPTER 20 USART Table 20.4-4 Function of each bit of the extended status/control register (ESCRn) Bit name Function bit14 LBD: • This bit goes 1 if a LIN synch break was detected in operating mode 3. Writing a 0 to LIN synch break it clears this bit and the corresponding interrupt, if it is enabled.

  • Page 498

    CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.4.6 Extended Communication Control Register (ECCRn) The extended communication control register provides bus idle recognition interrupt settings, synchronous clock settings, and the LIN break generation.

  • Page 499

    MB96300 Super Series Hardware Manual CHAPTER 20 USART ■ Extended communication control register (ECCRn) Figure 20.4-7 Configuration of the extended communication control register (ECCRn) ECCRn Initial value MS SCDE SSM 0 0 0 0 0 0 X X W R/W R/W bit0 Transmission bus idle TBI *...

  • Page 500

    CHAPTER 20 USART MB96300 Super Series Hardware Manual Table 20.4-6 Function of each bit of the Extended communication control register (ECCRn) Bit name Function bit7 INV: Invert serial • This bit inverts the serial data at SINn and SOTn pin. SCKn is not affected (see data ESCRn: SCES).

  • Page 501

    MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.4.7 Baud Rate/Reload Counter Register (BGRn) The baud rate/reload counter registers set the division ratio for the serial clock. Also the actual count of the transmission reload counter can be read. ■ Baud rate generator register (BGRn) Figure 20.4-8 Baud rate generator register (BGRn) Initial value 0 0 0 0 0 0 0 0...

  • Page 502

    CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.4.8 Extended Serial Interrupt Register (ESIRn) The extended serial interrupt register contains control bits to change the interrupt handling of the USART for improved interrupt handling and to enable DMA to handle USART data transfers.

  • Page 503

    MB96300 Super Series Hardware Manual CHAPTER 20 USART Table 20.4-7 Function of each bit of the extended serial interrupt register (ESIRn) Bit name Function bit3 TDRE: • This flag has the same function as SSR:TDRE but it is not cleared when data is Transmission Data written to the transmission data register TDR.

  • Page 504: Usart Interrupts

    CHAPTER 20 USART MB96300 Super Series Hardware Manual 20.5 USART Interrupts USART uses both reception and transmission interrupts. An interrupt request can be generated for either of the following causes: • Receive data is set in the Reception Data Register (RDRn), or a reception error occurs. •...

  • Page 505

    MB96300 Super Series Hardware Manual CHAPTER 20 USART ● Receive interrupt If one of the following events occurs in reception mode, the corresponding flag bit of the Serial Status Register (SSRn) and the Extended Serial Interrupt Register (ESIRn) is set to “1”: •...

  • Page 506

    CHAPTER 20 USART MB96300 Super Series Hardware Manual service routine. ● LIN Synchronization Break Interrupt This paragraph is only relevant, if USART operates in mode 3 as a LIN slave. If the bus (serial input) goes “0” (dominant) for more than 11 bit times, the LIN Break Detected (LBD) flag bit of the Extended Status/Control Register (ESCRn) is set to “1”.

  • Page 507

    MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.5.1 Receive interrupt Generation and Flag Set Timing The following are the receive interrupt causes: completion of reception (SSRn:RDRF) and occurrence of a reception error (SSRn:PE, ORE, or FRE). ■ Receive interrupt generation and flag set timing Generally a receive interrupt is generated, if the received data is complete (when ESIRn:AICD = "0": SSRn:RDRF = "1", when ESIRn:AICD = "1": ESIRn:RDRF = "1") and the receive interrupt Enable (RIE) flag bit of the Serial Status Register (SSRn) was set to “1”.

  • Page 508

    CHAPTER 20 USART MB96300 Super Series Hardware Manual Figure 20.5-2 ORE set timing: Receive data RDRF...

  • Page 509

    MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.5.2 Transmission Interrupt Generation and Flag Set Timing A transmission interrupt is generated when the transmission data is transferred from transmission data register (TDRn) to transmission shift register and started. ■ Transmission interrupt generation and flag set timing A transmission interrupt is generated, when the next data to be sent is ready to be written to the Transmission Data Register (TDRn), i.

  • Page 510

    CHAPTER 20 USART MB96300 Super Series Hardware Manual ■ Transmission interrupt request generation timing If the TDRE flag is set to “1” when a transmission interrupt is enabled (SSRn: TIE=1), transmission interrupt request is generated. Note: A transmission completion interrupt is generated immediately after the transmission interrupt is enabled (TIE=1) because the TDRE bit is set to 1 as its initial value.

  • Page 511: Usart Baud Rates

    MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.6 USART Baud Rates One of the following can be selected for the USART serial clock source: • Dedicated baud rate generator (Reload Counter) • External clock as it is (clock input to the SCKn pin) •...

  • Page 512

    CHAPTER 20 USART MB96300 Super Series Hardware Manual Figure 20.6-1 Baud rate selection circuit (reload counter) REST Start bit falling Reload Value: v edge detected Rxc = 0? Reception Reception Reload Clock 15-bit Reload Counter reset Rxc = v/2? Reload Value: v Peripheral clock CLKP1 Txc = 0?

  • Page 513

    MB96300 Super Series Hardware Manual CHAPTER 20 USART 20.6.1 Setting the Baud Rate This section describes how the baud rates are set and the resulting serial clock frequency is calculated. ■ Calculating the baud rate The both 16-bit reload counters are programmed by the baud rate generator registers (BGRn). The following calculation formula should be used to set the desired baud rate: Reload Value: v = [Φ...

  • Page 514

    CHAPTER 20 USART MB96300 Super Series Hardware Manual ■ Suggested division ratios for different peripheral clock CLKP1 frequencies and baud rates The following settings are suggested for different peripheral clock CLKP1 frequencies and baud rates: Table 20.6-1 Suggested baud rates and reload values at different peripheral clock CLKP1 frequencies. 8 MHz 10 MHz 16 MHz...

  • Page 515

    MB96300 Super Series Hardware Manual CHAPTER 20 USART 2) Maximum Synchronous Baud Rate: Peripheral