Table of Contents
Advertisement
CHAPTER 16 PROGRAMMABLE PULSE GENERATOR
Figure 16.1-2 Configuration diagram of Programmable Pulse Generator
MDSE
PCNn: bit 13
0
PWM operation
1
One shot
CKS1,0
PCNn: bit 11,10
0
0
CLK
0
1
CLK / 4
1
0
CLK / 16
1
1
CLK / 64
CLKP1
CLK
Prescaler
RLT6 underflow
CKSELi
GCN2g: bit i
0
RLT6 underflow
1
CLKP1
TSELi3,2,1,0 GCN1g: (bit i * 4 + 3,2,1,0)
0
0
0
0
EN0 bit (GCN2g register)
0
0
0
1
EN1 bit (GCN2g register)
0
0
1
0
EN2 bit (GCN2g register)
0
0
1
1
EN3 bit (GCN2g register)
16-bit Reload Timer 0
0
1
0
0
16-bit Reload Timer 1
0
1
0
1
External trigger (g + 0)
1
0
0
0
External trigger (g + 1)
1
0
0
1
External trigger (g + 2)
1
0
1
0
External trigger (g + 3)
1
0
1
1
Disabled
None of above
EN0
GCN2g: bit 0
EN1
GCN2g: bit 1
EN2
GCN2g: bit 2
EN3
GCN2g: bit 3
RLT 0 output
RLT 1 output
TTG
TTG
TTG
TTG
(g+0)
(g+1)
(g+2)
(g+3)
Note:
This diagram is also valid for the other available PPGs. For configuring RLT6 see CHAPTER 15 "16-
BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)".
RLT6 can be used as a normal RLT if it is not required for the PPG operation.
414
Period value
Duty value
PCSR
PDUT
Reload
Reload
Buffer
Buffer
Reload
PTMR
CNTE PCNn: bit 15
0
1
Control
circuit
RTRG PCNn: bit 12
0
1
STGR PCNn: bit 14
Edge
0
No effect
selection
1
Software trigger
EGS1,0
PCNn: bit 7,6
0
0
No effect
0
1
Rising edge
1
0
Falling edge
Both edges
1
1
MB96300 Super Series Hardware Manual
PGMS
OSEL
PCNn: bit 9, bit 0
0
0
Normal output
0
1
Inverted output
1
0
Clamped L output
1
Clamped H output
1
Output level
Compare
(Latch)
Stop
Enable operation
Restart disabled
Restart enabled
IRS1
IRS0
PCNn: bit 3, bit 2
0
0
Software trigger or trigger input
0
1
Counter borrow
1
0
Duty value match
1
1
Counter borrow or duty value match
General purpose port
or other port function
0
PPGn
1
OE PCNn: bit 1
0
PPG output disabled
1
PPG output enabled
IREN PCNn: bit 5
0
Interrupt disabled
1
Interrupt enabled
PPGn interrupt
IRQF PCNn: bit 4
0
No interrupt request
1
Interrupt request
Write 0: clear IRQF
Advertisement
Table of Contents
