Fujitsu MB96300 series Hardware Manual page 408

F2mc-16fx 16-bit
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CHAPTER 15 16-BIT RELOAD TIMER (WITH EVENT COUNT FUNCTION)
Table 15.2-1 Clock sources for CSL0/1 and FSEL bit settings (Continued)
FSEL
CSL1
1
1
0
1
[Bits 9, 8, 7] MOD2, MOD1, MOD0 (Operation mode and TINn function)
These bits set the operation mode and input pin (TINn) functions.
The MOD2 bit selects the input pin (TINn) function. When MOD2 = "0", the pin TINn is used as a
trigger input. In this case, the reload register content is loaded to the counter when an active edge is input
to the pin TINn and count operation proceeds. When MOD2 = "1", the timer operates in gated counter
mode and the pin TINn is used as a gate input. In this mode, the counter only counts while an active level
is input to the pin TINn.
Table 15.2-2 and table Table 15.2-3 list the MOD2/1/0 bit settings.
Table 15.2-2 MOD2/1/0 bit settings for internal clock mode (CSL0/1 = "00
MOD2
0
0
0
0
1
1
Table 15.2-3 MOD2/1/0 bit settings for event counter mode (CSL0/1 = "11
MOD2
x
Bits marked as x in the table can be set to any value.
400
CSL0
Clock Source (Time for peripheral clock CLKP1 = 24 MHz)
1
1
MOD1
MOD0
0
0
0
1
1
0
1
1
x
0
x
1
MOD1
MOD0
0
0
0
1
1
0
1
1
MB96300 Super Series Hardware
External event count mode
External event count mode / 2
Input Pin Function
Active Edge or Level
Trigger disabled
Trigger input
Gate input
Input Pin Function
Active Edge or Level
-
Event input
", "01
", or "10
")
B
B
B
-
Rising edge
Falling edge
Both edges
"L" level
"H" level
")
B
-
Rising edge
Falling edge
Both edges

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