Fujitsu MB96300 series Hardware Manual page 162

CHAPTER 6 CLOCKS
Table 6.2-2 Function Description of Each Bit of the Clock Monitor Register (CKMR) (1/2)
Bit name
bit 8 - SC1M0 and
bit 9 SC1M1:
System Clock 1
Monitor bits
bit 10 - SC2M0 and
bit 11 SC2M1:
System Clock 2
Monitor bits
bit 12 RCM:
RC Clock Monitor
bit
154
• These bits indicate which clock is currently used for the System Clock 1 according to
the following table:
bit9 bit8
SC1M1 SC1M0
0 0 CLKS1 is set to CLKRC (RC clock)
0 1 CLKS1 is set to CLKMC (Main clock)
1 0 CLKS1 is set to CLKPLL/CLKMOD (PLL clock)
1 1 CLKS1 is set to CLKSC (Sub clock)
• These bits show the currently active CPU clock mode.
• The read value of the SC1M bits can differ from the value written to the SC1S System
Clock 1 Select bits. This indicates that a requested clock mode transition has not been
completed yet.
• An ongoing transition of the clock mode (synchronization mechanism in effect) is
indicated as follows: Active clock mode shown by the SC1M bits differs from the
SC1S setting although clock selected by SC1S bits is ready (clock monitor bit '1').
The SC1M bits are updated after completion of the clock mode transition.
• Clock mode switching is not possible when the selected clock is not ready (clock
monitor bit of the clock selected by the SC1S bits is "0").
• These bits indicate which clock is currently used for the System Clock 2 according to
the following table:
bit11 bit10
SC2M1 SC2M0
0 0 CLKS2 is set to CLKRC (RC clock)
0 1 CLKS2 is set to CLKMC (Main clock)
1 0 CLKS2 is set to CLKPLL (unmodul. PLL clock)
1 1 CLKS2 is set to CLKSC (Sub clock)
• The read value of the SC2M bits can differ from the value written to the SC2S System
Clock 2 Select bits. This indicates that a requested clock mode transition has not been
completed yet.
• An ongoing transition of the clock mode (synchronization mechanism in effect) is
indicated as follows: Active clock mode shown by the SC2M bits differs from the
SC2S setting although clock selected by SC2S bits is ready (clock monitor bit '1').
The SC2M bits are updated after completion of the clock mode transition.
• Clock mode switching is not possible when the selected clock is not ready (clock
monitor bit of the clock selected by the SC2S bits is "0").
• This bit indicates if the internal RC oscillator is ready or not.
• RCM = "1" means that the RC oscillator is ready and can be used. If RCM = "1"
although RCE was set to "0", then the RC oscillator has not been disabled because the
RC clock is used for System Clock 1 or 2.
• RCM = "0" means that the RC oscillator is either disabled or the RC oscillation
stabilization time is in effect.
• Any reset initializes this bit to "0" and stops the operation of the MCU. After the RC
oscillation stabilization wait time, this bit is set to "1" and the operation of the MCU
resumes with the execution of the reset sequence.
Function
System Clock 1 Monitor bits
System Clock 2 Monitor bits