Fujitsu MB96300 series Hardware Manual page 116

CHAPTER 3 INTERRUPTS
Table 3.8-1 Control of interrupt acceptance priority
Event INT#
- Instruction Break
(VEIB)
system reserved
- Tool Break (VENMI)
system reserved
11 NMI
9 Address match
detection
(HW-INT9)
from Peripheral IRQ
13
on
12 Delayed INT
- Software Instruction
Break (INTE)
system reserved
9 INT9
10 Undefined instruction
exception
all INT instruction
- RETI instruction
IL and ILM: Interrupt level and mask
I:
108
Type Level
P2 Current instruction execution is
finished,
ILM>2 || P == 1
P2 Current instruction execution is
finished, string instruction is
interrupted,
ILM>2 || P == 1
P4 Current instruction execution is
finished, string instruction is
interrupted,
ILM>4 || P == 1
P6 Current instruction execution is
finished, string instruction is
interrupted,
ILM>6 || P == 1
IL Current instruction execution is
U0... finished, string instruction is
U7 interrupted,
ILM > IL
P == 1
I == 1
For multiple requests with same IL,
smallest IRQ number is accepted.
IL Current instruction execution is
U0... finished, string instruction is
U7 interrupted,
ILM > IL
P == 1
I == 1
No peripheral IRQs pending with
same IL.
P2 always accepted
-
-
-
-
Interrupt enable flag (Peripheral type interrupts)
MB96300 Super Series Hardware Manual
Acceptance condition Action, if accepted
Save CPU P = 0
status to ILM = 2
system stack
P = 0
S = 1
ILM = 2
Branch to
interrupt
vector
P = 0
ILM = 4
P = 0
ILM = 6
ILM = IL
ILM = IL
P = 0
ILM = 2
I = 0
I = 0
I = 0
I = 0
restore CPU status
(including P, I, S, ILM)