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MB96300 Super Series Hardware Manual
4.4
DMA Controller Operation
This section describes the DMA controller operation.
■ DMA Controller Operation
Figure 4.4-1 "DMAC Operation" shows the DMA controller operation.
Data transfer using DMA is performed in the following order:
1. The peripheral resource (I/O) requests DMA transfer by asserting an interrupt.
2. When the corresponding bit of the DMA Enable Register (DER:EN) is "1" and the interrupt number
matches the setting of the DISEL register, DMAC references from the descriptor the transfer source
address, destination address, count and configuration of the channel.
3. DMA data transfer is started between I/O and memory.
4. DMA descriptors are updated.
5. After one item transferred (either Byte data or Word data)
(a) Transfer has not been completed (DCT does not reach 0):
DMAC clears the DMA transfer request (interrupt) of the peripheral resource.
(b) At transfer end (DCT reaches 0):
After completion of DMA transfer, the flag indicating completion of the transfer is set in the DMA Status
Register (DSR:DTE bit), outputting an interrupt request to the interrupt controller.
Figure 4.4-1 DMAC Operation
IOA
I/O register
(3)
BAP
Buffer
IOA:
BAP:
DCT:
Peripheral function (I/O)
I/O register
IRQ
(5a)
(1)
DMA controller
(2)
(5b)
CPU
Interrupt controller
I/O address pointer
Buffer address pointer
Data counter
CHAPTER 4 DMA
DMA
descriptor
(4)
133
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