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CHAPTER 20 USART
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LIN Synch Break Generation Circuit
The LIN break generation circuit generates a LIN break of a determined length.
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Bus Idle Detection circuit
The bus idle detection circuit recognizes if neither reception nor transmission is going on. In this case, the
circuit generates the special flag bits TBI and RBI.
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LIN-USART Serial Mode Register (SMRn)
This register performs the following operations:
• Selecting the LIN-USART operation mode
• Selecting a clock input source
• Selecting if an external clock is connected "one-to-one" or connected to the reload counter
• Resetting dedicated reload timer
• Resetting the LIN-USART (preserving the settings of the registers)
• Specifying whether to enable serial data output to the corresponding pin
• Specifying whether to enable clock output to the corresponding pin
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Serial Control Register (SCRn)
This register performs the following operations:
• Specifying whether to provide parity bits
• Selecting parity bits
• Specifying a stop bit length
• Specifying a data length
• Selecting a frame data format in mode 1
• Clearing the error flags
• Specifying whether to enable transmission
• Specifying whether to enable reception
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Serial Status Register (SSRn)
This register performs the following functions:
• Indicating status of receive/transmit operations and errors
• Specifying LSB first or MSB first
• Receive interrupt enable/disable
• Transmit interrupt enable/disable
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Extended Status/Control Register (ESCRn)
This register performs the following functions:
• LIN synch break interrupt enable/disable
• Indicating LIN synch break detection
• Specifying LIN synch break length
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MB96300 Super Series Hardware Manual
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