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CHAPTER 20 USART
Table 20.4-1 Functions of each bit of control register (SCRn)
Bit name
bit14
P:
Parity selection bit
bit13
SBL:
Stop bit length
selection bit
bit12
CL:
Data length selection
bit
bit11
AD:
Address/Data
selection bit
bit10
CRE:
Clear reception error
flags bit
bit9
RXE:
Reception enable bit
bit8
TXE:
Transmission enable
bit
478
When parity is provided and enabled this bit selects even (0) or odd (1) parity.
This bit selects the length of the stop bit of an asynchronous data frame or a
synchronous frame if SSM of the ECCRn is selected. This bit is fixed to 0 (1 stop bit) in
mode 3 (LIN).
This bit specifies the length of transmission or reception data. This bit is fixed to 1 (8
bits) in mode 2 and 3.
This bit specifies the data format in multiprocessor mode 1. Writing to this bit is
provided for a master CPU, reading from it for slave CPU. A 1 indicates an address
frame, a 0 indicates a usual data frame.
Note:
Please read the hints about using this bit in Section 20.8 "Notes on Using USART".
This bit clears the FRE, ORE, and PE flag of the Serial Status Register (SSRn) and
resets any ongoing reception.
Writing a 1 to it clears the error flag.
Writing a 0 has no effect.
Reading from it always returns 0.
Note:
Clear reception error flags after the receive operation.
This bit enables/disables LIN-USART reception.
If this bit is set to 0, USART disables the reception of data frames.
If this bit is set to 1, USART enables the reception of data frames.
The LIN synch break detection in mode 3 remains unaffected.
Note:
If reception is disabled (RXE=0) during receiving, it is stopped immediately. In this
case, data is not guaranteed.
This bit enables/disables LIN-USART transmission.
If this bit is set to 0, USART disables the transmission of data frames.
If this bit is set to 1, USART enables the transmission of data frames.
Note:
If transmission is disabled (TXE=0) during transmitting, it is stopped immediately.
In this case, data is not guaranteed.
MB96300 Super Series Hardware Manual
Function
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