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MB96300 Super Series Hardware Manual
22.8.2
Transmission Request Registers (TREQR1n, TREQR2n)
The Transmission Request Registers (TREQR1n, TREQR2n) control the transmission of
message objects.
■ Transmission Request Registers (TREQR1n, TREQR2n)
Figure 22.8-2 Transmission Request Registers (TREQR1n, TREQR2n)
Transmission Req Register 1 high byte
Address : Base + 0x81
Transmission Req Register 1 low byte
Address : Base + 0x 80
Transmission Req Register 2 high byte
Address : Base + 0x83
Transmission Req Register 2 low byte
Address : Base + 0x 82
■ Function of the Transmission Request Registers (TREQR1n, TREQR2n)
TXRQST32-1
Transmission Request Bits (of all Message Objects)
0
This Message Object is not waiting for transmission.
1
The transmission of this Message Object is requested and is not yet done.
These registers hold the TXRQST bits of the 32 Message Objects. By reading out the TXRQST bits, the CPU
can check for which Message Object a Transmission Request is pending. The TXRQST bit of a specific
Message Object can be set/reset by the CPU via the IFx Message Interface Registers or by the Message
Handler after reception of a Remote Frame or after a successful transmission.
Note:
When the lowest priority message buffer is used for transmission, setting TXRQST = "0" may cause a
delay of transmission, when TXRQST is set to "1" again.
Depending on the exact time when TXRQST was set to 0, the message may not be transmitted
15
14
H
Read/write ⇒
(R)
(R)
(0)
(0)
Default value⇒
7
6
H
Read/write ⇒
(R)
(R)
(0)
(0)
Default value⇒
15
14
H
Read/write ⇒
(R)
(R)
(0)
(0)
Default value⇒
7
6
H
Read/write ⇒
(R)
(R)
(0)
(0)
Default value⇒
CHAPTER 22 CAN CONTROLLER
13
12
11
10
9
TXRQST16-9
(R)
(R)
(R)
(R)
(R)
(0)
(0)
(0)
(0)
(0)
5
4
3
2
TXRQST8-1
(R)
(R)
(R)
(R)
(R)
(0)
(0)
(0)
(0)
13
12
11
10
9
TXRQST32-25
(R)
(R)
(R)
(R)
(R)
(0)
(0)
(0)
(0)
(0)
5
4
3
2
TXRQST24-17
(R)
(R)
(R)
(R)
(R)
(0)
(0)
(0)
(0)
⇐ Bit no.
8
TREQR1Hn
(R)
(0)
⇐ Bit no.
1
0
TREQR1Ln
(R)
(0)
(0)
⇐ Bit no.
8
TREQR2Hn
(R)
(0)
⇐ Bit no.
1
0
TREQR2Ln
(R)
(0)
(0)
613
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