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CHAPTER 21 400 kHz I
W
R/W
■ Bus control register (IBCRn) contents
552
2
C INTERFACE
Figure 21.2-3 Configuration of the bus control register (IBCRn)
15
14
13
12
11
10
BER BEIE SCC MSS
ACK GCAA INTE
R/W R/W W R/W
R/W
R/W
:
Write only bit
Readable and writable
:
:
Initial value
9
8
IBCRn
INT
Initial value
0 0 0 0 0 0 0 0
R/W R/W
bit 8
INT
0
1
bit 9
INTE
0
Interrupt disabled
1
Interrupt enabled
bit 10
GCAA
0
No acknowledge on general call address
1
Acknowledge on general call address
bit 11
ACK
0
No Acknowledge on data byte reception
1
Acknowledge on data byte reception
bit 12
MSS
0
Go to slave mode
1
Go to master mode (s. table below for details)
bit 13
SCC
0
Write: No effect:
1
Write: Generate repeated start condition
bit 14
BEIE
0
Bus error interrupt disabled
1
Bus error interrupt enabled
bit 15
BER
0
Clear bus error int.
1
No effect
B
Interrupt bit
see table on next page for details
Interrupt enable bit
Generall call address acknowledge bit
Acknowledge bit
Master slave select bit
Start condition continue bit
Bus error interrupt enable bit
Bus error bit
write
read
No error detected
Error detected
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