I/O Port Registers - Fujitsu MB96300 series Hardware Manual

MB96300 Super Series Hardware Manual
13.2

I/O Port Registers

Each general purpose port pin GPxx is controlled by nine types of registers. These are:
• Port Data Register (PDR00 to PDRnn)
• External Pin State Register (EPSR00 to EPSRnn)
• Port Direction Register (DDR00 to DDRnn)
• Port Input Enable Register (PIER00 to PIERnn)
• Port Input Level Register (PILR00 to PILRnn)
• Extended Port Input Level Register (EPILR00 to EPILRnn)
• Port Output Drive Register (PODR00 to PODRnn)
• Port High Drive Register (PHDR00 to PHDRnn)
• Pull-Up Control Register (PUCR00 to PUCRnn)
■ I/O port registers
The general purpose port pin GPxx_y is controlled by bit y of the I/O port register xx. For example, the data
direction of port pin GPxx_y is controlled by DDRxx_y.
Bit 7 6
P7 P6
PS7 PS6
D7 D6
IE7 IE6
IL7 IL6
EIL7 EIL6
OD7 OD6
HD7 HD6
PU7 PU6
Figure 13.2-1 I/O port registers (only shown for port 00)
5 4 3 2
P5 P4 P3 P2
PS5 PS4 PS3 PS2
D5 D4 D3 D2
IE5 IE4 IE3 IE2
IL5 IL4 IL3 IL2
EIL5 EIL4 EIL3 EIL2
OD5 OD4 OD3 OD2
HD5 HD4 HD3 HD2
PU5 PU4 PU3 PU2
1 0
P1 P0 Port 0 Data Register (PDR00)
PS1 PS0 Port 0 External Pin State Register (EPSR00)
D1 D0 Port 0 Direction Register (DDR00)
IE1 IE0 Port 0 Input Enable Register (PIER00)
IL1 IL0 Port 0 Input level Register (PILR00)
EIL1 EIL0 Port 0 Extended Input Level Register (EPILR00)
OD1 OD0 Port 0 Output Drive Register (PODR00)
HD1 HD0 Port 0 High Drive Register (PHDR00)
PU1 PU0 Port 0 Pull-Up Control Register (PUCR00)
CHAPTER 13 I/O PORTS
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