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the corresponding enable bit in the CKSR register to "1". After stabilization of the activated clock, the
corresponding Clock monitor bit of the CKMR register is set and indicates the clock as "ready".
• The Main clock must be enabled if the PLL clock should be enabled (The setting of PCE has no effect
when MCE is set to "0").
• Setting MCE to "0" does not disable the Main oscillator when System clock 1 or 2 is set to Main or PLL
clock because the Main clock is the input signal for the PLL multiplier circuit.
CHAPTER 6 CLOCKS
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