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CHAPTER 8 RESETS AND STARTUP
Table 8.5-1 Function Description of Each Bit of the Reset Configuration Register (RCR) (3/3)
Bit name
bit 5
SCSDI:
Sub Clock Stop
Detection Interval
select bit
bit 6 -
Reserved
bit 7
212
• This bit controls the measurement interval of the Sub clock stop detection circuit.
• This bit is initialized to "0" by any reset.
• Writing "0" to this bit sets the interval time to 384 - 512 RC clock cycles.
• Writing "1" to this bit sets the interval time to 24 - 32 RC clock cycles.
• The Sub clock stop detection circuit sets the Sub clock missing flag (RCCSR: SCMF)
if no rising edge of the Sub clock input signal (CLKSC) was observed within the
selected interval time.
• Always write "0" to these bits.
• The read value of these bits is undefined.
• Read modify write operations to this register are not affected.
MB96300 Super Series Hardware Manual
Function
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