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MB96300 Super Series Hardware Manual
bit1: Enable interrupt requests at half-second (500ms) intervals
When the 21-bit counter overflows, this flag is set to "1".
INTE4
0
No interrupt requests
1
Generate interrupt requests at half-second (500 ms) intervals.
bit0: half-second (500ms) interrupt request flag
INT4
0
No interrupt requests
1
Generate interrupt requests at half-second
(500 ms) intervals.
■ Clock Select Register (WTCKSR)
The Clock Select Register is used to select the clock source for Real Time Clock.
15
14
13
WTCKSR
-
-
-
-
-
-
R/W
: Readable and writable
W
: Write only
X
: undefined value
-
: undefined
: Initial value
Note:
WTCKSR is initialized by all reset causes except for unused bits.
Application Notes:
When the setting of WTCKR:CKSEL[1:0] shall be changed, the clock on which the Real time clock is
currently running must stay enabled for at least 3 further cycles after change. Otherwise
the Real time clock does not change to the new setting. The former clock can be switched
off afterwards.
Example: Real time clock shall be changed from Main clock to RC-Clock:
Main clock oscillator is enabled after power on. Therefore is must be enabled when WTCKSR:CKSEL[1:0]
is changed to 'RC clock' by writing '10' to it. Otherwise RTC cannot switch to RC clock. The Main
oscillator must stay enabled for at least three Main clock cycles after the write access to
WTCKST:CKSEL[1:0].
Read
Figure 24.2-4 Clock Select Register (WTCKSR)
12
11
10
9
8
-
-
-
CKSEL1 CKSEL0
-
R/W
-
-
R/W
bit 9, 8
CKSEL[1:0]
00
01
10
11
CHAPTER 24 REAL TIME CLOCK
Operation
Status
Write
Clear the flag.
Writing does not affect the operation.
Initial value
- - - - - - 0 0
B
Real time clock clock select bit
Main clock (CLKMC) used
Sub clock (CLKSC) used
RC clock (CLKRC) used
prohibited
647
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