Fujitsu MB96300 series Hardware Manual page 835

F2mc-16fx 16-bit

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MB96300 Super Series Hardware Manual

Table 31.2-4 Function of each bit of the EDSU register

This bit enables INT9 for the transmit interrupt of the selected communication

• Writing '0' - The INT9 generation on transmit IRQ is disabled.

• Writing '1' - The INT9 generation on transmit IRQ is enabled.

• The bit can be read and written.

The TIE bit is cleared after reset.

This bit reﬂects the actual status of the transmit interrupt ﬂag of the selected

communication device

• The bit is read only.

• Writing is ignored.

• To clear the interrupt ﬂag, use the according interrupt ﬂag in the selected

communication device (peripheral resource).

The initial value depends on the selected communication device. See the

speciﬁcation of the according peripheral resource.

These bits select the monitor debugger communication device.

• USART 0, USART 1, USART 2 and USART 3 can be selected according to the

table below.

• These bits can be read and written.

The SEL bits are initialized with 0 after reset.

This bit enables INT9 for the receive interrupt of the selected communication

• Writing '0' - The INT9 generation on receive IRQ is disabled.

• Writing '1' - The INT9 generation on receive IRQ is enabled.