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Table 6.2-1 Function Description of Each Bit of the Clock Selection Register (CKSR) (2/3)
Bit name
bit 12
RCE:
RC Clock Enable
bit
bit 13
MCE:
Main Clock Enable
bit
bit 14
PCE:
PLL Clock Enable
bit
•
This bit is used to enable/stop the internal RC oscillator.
• Writing "1" to this bit enables the RC oscillator and writing "0" stops the oscillator.
• This bit is initialized to "1" (oscillator on) by each reset.
• The RC oscillation stabilization time is applied after enabling the RC oscillator. This
time is fixed to 64 RC clock cycles. After this time has elapsed, the RC clock monitor
bit (RCM) in the CKMR register is set.
• Selecting CLKRC as clock source for CLKS1 or CLKS2 activates the RC oscillator
independently of the setting of the RCE bit. The oscillator can only be stopped when
both System clocks are running with a different clock source.
Note:
•
Do not disable the RC oscillator if the Clock stop detection reset is enabled. Setting
RCE to "0" in this case causes a Clock stop detection reset.
• Do not disable the RC oscillator if the clock source for the Watchdog is set to RC
clock. Setting RCE to "0" in this case causes a Watchdog reset.
•
This bit is used to enable/stop the Main oscillation circuit.
• Writing "1" to this bit enables the Main oscillator and writing "0" stops the oscillator.
• This bit is initialized to "1" (oscillator on) by each reset.
• The Main oscillation stabilization time is applied after enabling the Main oscillator.
This time is defined by the MCST bits of the CKSSR register. After this time has
elapsed, the Main clock monitor bit (MCM) in the CKMR register is set.
• Selecting CLKMC, CLKPLL or CLKMOD as clock source for CLKS1 or CLKS2
activates the Main oscillator independently of the setting of the MCE bit. The
oscillator can only be stopped when both System clocks are running with different
clock sources.
• Setting this bit to "0" also disables the PLL clock (independently of the PCE setting)
and sets PCM to "0" unless the PLL clock is used as System clock 1 or 2.
Note:
• Do not disable the Main oscillator if the clock source for the Watchdog is set to Main
clock. Setting MCE to "0" in this case causes a Watchdog reset.
•
This bit is used to enable/stop the PLL oscillation circuit.
• Writing "1" to this bit enables the PLL and writing "0" stops the PLL.
• MCE must also be set to "1" if the PLL should be enabled because the PLL is using
the Main clock as input clock. For MCE = "0", the setting of PCE has no effect.
• This bit is initialized to "0" (PLL stopped) by each reset.
• The PLL stabilization time is applied after stabilization of the Main clock (MCM =
"1") and enabling of the PLL. This time is defined by the PCST bit of the CKSSR
register. After this time has elapsed, the PLL clock monitor bit (PCM) in the CKMR
register is set.
• Selecting CLKPLL or CLKMOD as clock source for CLKS1 or CLKS2 activates the
PLL independently of the setting of the PCE bit. The PLL can only be stopped when
both System clocks are running with different clock sources.
Function
CHAPTER 6 CLOCKS
151
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