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- Page 1 Fujitsu Microelectronics Europe MCU-AN-300055-E-V10 Application Note F²MC-FR FAMILY 32-BIT MICROCONTROLLER MB91460 INTERRUPTS APPLICATION NOTE...
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Page 2: Revision History
INTERRUPTS Revision History Revision History Date Issue 2008-02-06 First Version; MPi This document contains 26 pages. MCU-AN-300055-E-V10 - 2 - © Fujitsu Microelectronics Europe GmbH... -
Page 3: Warranty And Disclaimer
Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in original packing and without further defects resulting from the customer’s use or the transport. -
Page 4: Table Of Contents
Interrupt Vector Table .............. 13 2.5.3 Interrupt Control Register (ICR00-63) ............ 13 2.5.4 Hold Request Cancel Level Register (HRCL)..........13 Non-maskable Interrupt (NMI) ................14 3 INTERRUPT RECOMMENDATIONS AND EXAMPLES ..........15 MCU-AN-300055-E-V10 - 4 - © Fujitsu Microelectronics Europe GmbH... - Page 5 Setting global Interrupt Level ................. 16 Enabling and Disabling Interrupts globally ............. 17 Order of Initialization ..................... 18 Interrupt Vector Relocation..................19 4 ADDITIONAL INFORMATION ..................24 LIST OF TABLES....................... 25 LIST OF FIGURES ......................26 © Fujitsu Microelectronics Europe GmbH - 5 - MCU-AN-300055-E-V10...
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Page 6: Introduction
• Peripheral Interrupts • Exceptions such as Undefined Instruction • Traps such as INT instruction, Step Trace • Non-maskable Interrupt (NMI) • DMA can be used with most of the interrupts MCU-AN-300055-E-V10 - 6 - © Fujitsu Microelectronics Europe GmbH... -
Page 7: Interrupt Types
ISR execution has finished. Undefined instruction ISR can not also be interrupted by NMI and Traps. The System Stack Pointer is enabled (CCR:S = 0). xx: 00 to 63 © Fujitsu Microelectronics Europe GmbH - 7 - MCU-AN-300055-E-V10... -
Page 8: Traps
Interrupts etc.) can be used to initiate DMA transfers regardless of the status of the I flag and the interrupt level. For detailed information please refer to the DMA application note MCU-AN-300059. MCU-AN-300055-E-V10 - 8 - © Fujitsu Microelectronics Europe GmbH... -
Page 9: Interrupt Acceptance, Levels And Modes
7 & 8 No Level Save CPU status to system Exception stack S = 0 (use system stack) I = 0 i.e. all peripheral interrupts are suspended until Coprocessor Exception ISR © Fujitsu Microelectronics Europe GmbH - 9 - MCU-AN-300055-E-V10... -
Page 10: Interrupt Latency
These timing gets worsened if the stack / interrupt vector / ISRs are located in the external memory. This is because the wait cycles for external bus transfer get added to the above mentioned cycles. MCU-AN-300055-E-V10 - 10 - © Fujitsu Microelectronics Europe GmbH... -
Page 11: Registers
The Level can be set in C with the language extension directive __set_il(n), where n is the level. The machine instruction for this is MOV ILM,#n. Peripheral Interrupts disabled if the ICR is set to this value. © Fujitsu Microelectronics Europe GmbH - 11 - MCU-AN-300055-E-V10... -
Page 12: Condition Code Register (Ccr)
These bits hold intermediate data during the execution of step division. Step Trace Trap Flag. Setting this bit enables step trace trap. Its used by the emulator. Table 2-6: System Condition Code Register MCU-AN-300055-E-V10 - 12 - © Fujitsu Microelectronics Europe GmbH... -
Page 13: Interrupt Vector Table
ISR executes. Upon execution of RETI instruction the DMA would gain access to the D-Bus again (provided the MHALTI flag and the corresponding peripheral interrupt flag is cleared in the ISR). © Fujitsu Microelectronics Europe GmbH - 13 - MCU-AN-300055-E-V10... -
Page 14: Non-Maskable Interrupt (Nmi)
LOW level for 1 CLKP cycle then NMI is generated. In order to clear the NMI the MHALTI flag of HRCL register needs to be cleared after the level of the signal appearing on the NMIX pin changes to HIGH. MCU-AN-300055-E-V10 - 14 - © Fujitsu Microelectronics Europe GmbH... -
Page 15: Interrupt Recommendations And Examples
Please make sure to always define the complete interrupt vector table in just one C module and do not split it. /* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ /* ELIGIBILITY FOR ANY PURPOSES. -
Page 16: Reading An Interrupt Level
If the currently configured level of the peripheral can be read by reading out the corresponding ICR. /* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ /* ELIGIBILITY FOR ANY PURPOSES. -
Page 17: Enabling And Disabling Interrupts Globally
INTERRUPTS Chapter 3 Interrupt Recommendations and Examples /* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ /* ELIGIBILITY FOR ANY PURPOSES. (C) Fujitsu Microelectronics Europe GmbH /*---------------------------------------------------------------------------*/ __set_il(20);... -
Page 18: Order Of Initialization
For the Interrupt initialization the order of the steps has to be done like in the following example code. /* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ /* ELIGIBILITY FOR ANY PURPOSES. -
Page 19: Interrupt Vector Relocation
HIGHLY recommended that the entire vector table is relocated to RAM. This is because if in case any unhandled interrupt occurs then the software would crash. © Fujitsu Microelectronics Europe GmbH - 19 - MCU-AN-300055-E-V10... - Page 20 This is considering later the vector table is relocated to RAM starting from address 0x00032000. /* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ /* ELIGIBILITY FOR ANY PURPOSES.
- Page 21 In order to copy the section from Flash to RAM, I_RAM define in the Start91460.asm should be set to ON. /* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ /* ELIGIBILITY FOR ANY PURPOSES.
- Page 22 The following code does the interrupt level configuration and vector configuration. /* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ /* ELIGIBILITY FOR ANY PURPOSES.
- Page 23 6. Restore the original TBR value. The below code demonstrates the actual relocation of vector table. /* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */ /* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */ /* ELIGIBILITY FOR ANY PURPOSES.
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Page 24: Additional Information
INTERRUPTS Chapter 4 Additional Information 4 Additional Information Information about FUJITSU Microcontrollers can be found on the following Internet page: http://mcu.emea.fujitsu.com/ The software example related to this application note is: 91460_intvect It can be found on the following Internet page: http://mcu.emea.fujitsu.com/mcu_product/mcu_all_software.htm... -
Page 25: List Of Tables
Table 2-3: Processor Status....................11 Table 2-4: Interrupt Level Mask.................... 11 Table 2-5: Condition Code Register ..................12 Table 2-6: System Condition Code Register ................ 12 Table 2-7: Interrupt Control Register ..................13 © Fujitsu Microelectronics Europe GmbH - 25 - MCU-AN-300055-E-V10... -
Page 26: List Of Figures
INTERRUPTS List of Figures List of Figures Figure 3-1: IRAM Section Setting ..................20 Figure 3-2: @IRAM Section Setting..................21 MCU-AN-300055-E-V10 - 26 - © Fujitsu Microelectronics Europe GmbH...