Fujitsu MB96300 series Hardware Manual page 293

MB96300 Super Series Hardware Manual
Table 11.2-1 Function Description of Each Bit of the Watchdog Timer Configuration register (WDTC) (2/2)
Bit name
bit 4 - WTCS0 to
bit 5 WTCS1:
Watchdog Timer
Clock Selection
bits
bit 6 RSTP:
Watchdog Reset
at transition to
Stop mode
bit 7 Reserved
CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET
• These bits select the clock source for the Watchdog Timer according to the following
table:
bit4 bit3
WTCS1 WTCS0 Watchdog Timer Clock Selection bits
CLKWT = CLKRC (internal RC oscillation clock,
RC clock frequency can be changed during
0 0
Watchdog operation)
CLKWT = CLKRC (internal RC oscillation clock,
changing RC clock frequency during Watchdog
0 1
operation causes Watchdog reset)
1 0 CLKWT = CLKMC (Main oscillation clock)
1 1 CLKWT = CLKSC (Sub oscillation clock)
• These bits are initialized to "00" by any reset.
• It is not possible to change the setting of these bits after activation of the Watchdog reset
function (by first writing to the Watchdog Timer Clear Pattern register). Configuring
these bits and activating the Watchdog reset function with one 16 bit write access
however is possible.
• After a reset, these bits can be written again.
• Setting WTCS[1:0] to "00" selects the internal RC oscillator and it is possible to change
the RC clock frequency (by writing to CKFCR: RCFS bit) after activation of the
Watchdog reset function. Please note that changing the RC clock frequency also changes
the Watchdog interval time.
• Setting WTCS[1:0] to "01" also selects the internal RC oscillator, but it is NOT allowed
to change the RC clock frequency (by writing to CKFCR: RCFS bit) after activation of
the Watchdog reset function. Changing the RC clock frequency in this case causes a
Watchdog reset.
• This bit is initialized to "0" by any reset.
• It is not possible to change the setting of this bit after activation of the Watchdog reset
function (by first writing to the Watchdog Timer Clear Pattern register). Configuring this
bit and activating the Watchdog reset function with one 16 bit write access however is
possible.
• After a reset, this bit can be written again.
• When this bit is set to "0", then transition to Stop mode is allowed
• When this bit is set to "1", then writing "11" to SMCR: SMS (Stop mode) causes a
Watchdog reset.
• Set this bit to "1" only when the application is not using the Stop mode.
• Always write "0" to this bit.
• The read value of this bit is undefined.
• Read modify write operations to this register are not affected.
Function
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