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MB96300 Super Series Hardware Manual
■ Registers for A/D converter
A/D control status register ( Upper)
A/D control status register (
Data register (
Data register (
A/D setting register (
A/D setting register ( Lower)
A/D extended configuration register
Analog input enable register
Figure 18.2-1 Registers of the A/D Converter
15
14
BUSY
INT
Read/write
(R/W)
(R/W)
Initial value
(0)
(0)
Lower)
7
6
MD1
MD0
Read/write
(R/W)
(R/W)
Initial value
(0)
(0)
Upper)
15
14
-
-
Read/write
( - )
( - )
Initial value
(0)
(0)
Lower)
7
6
D7
D6
Read/write
(R)
(R)
Initial value
(0)
(0)
Upper)
15
14
ST2
ST1
Read/write
(R/W)
(R/W)
Initial value
(0)
(0)
7
6
ANS2 ANS1 ANS0 ANE4 ANE3 ANE2 ANE1 ANE0
Read/write
(R/W)
(R/W)
Initial value
(0)
(0)
7
6
-
-
Read/write
( - )
( - )
Initial value
(X)
(X)
7
6
ADE(x-1) ADE(x-2) ADE(x-3) ADE(x-4) ADE(x-5) ADE(x-6) ADE(x-7)
Read/write
( R/W )
( R/W )
Initial value
(0)
(0)
13
12
11
10
INTE
PAUS STS1
STS0
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(0)
5
4
3
2
-
-
-
S10
(R/W)
( - )
( - )
( - )
(0)
(X)
(X)
(X)
13
12
11
10
-
-
-
-
( - )
( - )
( - )
( - )
(0)
(0)
(0)
(0)
5
4
3
2
D5
D4
D3
D2
(R)
(R)
(R)
(R)
(0)
(0)
(0)
(0)
13
12
11
10
ST0
CT2
CT1
CT0
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(0)
5
4
3
2
(R/W)
(R/W)
(R/W)
(R/W)
(0)
(0)
(0)
(0)
5
4
3
2
-
-
-
LSEL
( - )
( - )
( - )
( R/W )
(X)
(X)
(X)
(0)
5
4
3
2
( R/W )
( R/W )
( R/W )
( R/W )
(0)
(0)
(0)
(0)
CHAPTER 18 A/D CONVERTER
Bit No.
9
8
STRT
-
ADCSH
(W)
( - )
(0)
(X)
1
0
Bit No.
-
ADCSL
reserved
( - )
( - )
(X)
(0)
Bit No.
9
8
ADCRH
D9
D8
(R)
(R)
(0)
(0)
1
0
Bit No.
D1
D0
ADCRL
(R)
(R)
(0)
(0)
Bit No.
9
8
ADSRH
ANS4 ANS3
(R/W)
(R/W)
(0)
(0)
1
0
Bit No.
ADSRL
(R/W)
(R/W)
(0)
(0)
1
0
Bit No.
ADECR
HSEL ADSEL
( R/W )
( R/W )
(0)
(0)
1
0
Bit No.
ADER(x/8)
ADE(x-8)
( R/W )
( R/W )
(0)
(0)
437
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