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CHAPTER 22 CAN CONTROLLER
22.6.1
IFx Command Request Registers (IFxCREQn)
A message transfer is started as soon as the CPU has written the message number to the
Command Request Register (IFxCREQn). With this write operation the CPU is notified
that a transfer is in progress. If a CPU access to the CAN happens while the transfer is in
progress then this access is delayed until the transfer has finished. After 3 to 6 CAN_CLK
periods, the transfer between the Interface Register and the Message RAM has
completed and the upcoming CPU access is executed.
■ IFx Command Request Registers (IFxCREQn)
Figure 22.6-1 Configuration of the IFx Command Request Registers (IFxCREQn)
IFx Command Request Register high byte
Address (x = 1): CANn base + 0x11
(x = 2): CANn base + 0x41
Read/write ⇒ (R/(W)) (R)
Default value⇒
IFx Command Request Register low byte
Address (x = 1): CANn base + 0x 10
(x = 2): CANn base + 0x 40
Default value⇒
■ Function of the IFx Command Request Registers (IFxCREQn)
[bit15]
BUSY
0
1
[bit14-bit8]
res
[bit5-bit0]
MSGN
0x00
0x01-0x20
0x21-0xFF
[bit5-bit0]
MSGN
0x00
0x01-0x40
0x41-0xFF
598
15
14
H
BUSY res
H
(0)
(X)
7
6
H
H
Read/write ⇒
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
Busy Flag
Reset to zero when read/write action has finished
Set to one when writing to the IFx Command Request Register
Reserved Bits
Always write "0". Read value is not defined. Read-Modify-Write is not affected.
Message Number (for 32 message buffer CANs, please refer to the data sheet for the number of message buffers
Not a valid Message Number, interpreted as 0x20.
Valid Message Number, the Message Object in the Message RAM is selected for data transfer.
Not a valid Message Number, interpreted as 0x01-0x1F.
Message Number (for 64 message buffer CANs, , please refer to data sheet for the number of message buffers of
Not a valid Message Number, interpreted as 0x20.
Valid Message Number, the Message Object in the Message RAM is selected for data transfer.
Not a valid Message Number, interpreted as 0x01-0x3F.
MB96300 Super Series Hardware Manual
13
12
11
10
9
res
res
res
res
res
(R)
(R)
(R)
(R)
(R)
(X)
(X)
(X)
(X)
(X)
5
4
3
2
MSGN
(0)
(0)
(0)
(0)
of the device.)
the device.)
⇐ Bit no.
8
IFxCREQHn
res
(R)
(X)
⇐ Bit no.
1
0
IFxCREQLn
(0)
(1)
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