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CHAPTER 31 MEMORY PATCH FUNCTION
■ EDSU extension register (EDSU)
EDSU
R/W : Readable and writable
R
: Read only
To avoid the implementation of the debug services directly in the kernel of the application, external event
must be handled by the system to trigger the debug services. For further information regarding the debug
system, refer to the boot ROM specifications.
The EDSU extension register (EDSU) controls the embedded debug support, based on the address and data
match functions. There are mainly two functions controlled by this register:
• General enable the hardware trigger of INT9 for debug functions (EDSU:EN).
• Select a communication interface; its receive and/or transmit interrupt is able to trigger an INT9 exception
to realize a break on request of this interface (EDSU:SEL, EDSU:TIE, EDSU:TINT, EDSU:RIE,
EDSU:RINT). For extended capabilities of the break interrupt selection, see the description of the EDSU2
register.
For a detailed description of the control and status bits of EDSU refer to Table 31.2-4.
The interrupt vector of the INT9 can be configured to be located at a fixed address (0x0FFFD8), to be at a
location independent from the value of the table base register (TBR). For details about fixing the vector
address of INT9, please refer to the chapter "Interrupts", "NMI control status register (NMI)". This option is
used to increase the reliability of a debug system making use of the EDSU functions.
Table 31.2-4 Function of each bit of the EDSU register
Name
bit 15
bit 14
826
Figure 31.2-4 EDSU extension register (EDSU)
15
14
Address:
-
EN
0003AF
H
Access:
R/W
-
R/W R R/W
EN
The enable bit EN controls the generation of hardware INT9 requests of the
embedded debug system. It enables the interrupt generation of the address match
detection, data value match detection and of the selected communication device
receive interrupt in general. The memory patch function is not affected by this bit.
• Writing '0' - Disables embedded debug support.
• Writing '1' - Enables embedded debug support.
• The bit can be read and written.
The EN bit is cleared after reset.
-
Unused bit.
• Read returns undefined value.
• Writing to this bit is ignored.
MB96300 Super Series Hardware Manual
13
12
11
10
9
8
TIE TINT SEL1
SEL0 RIE RINT
R/W R/W R
Function
Initial value
0X0X000X
B
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