Usart Interrupts - Fujitsu MB96300 series Hardware Manual

CHAPTER 20 USART
20.5

USART Interrupts

USART uses both reception and transmission interrupts. An interrupt request can be
generated for either of the following causes:
• Receive data is set in the Reception Data Register (RDRn), or a reception error occurs.
• Transmission data is transferred from the Transmission Data Register (TDRn) to the
transmission shift register and started.
• A LIN break is detected
DMA is available for these interrupts.
■ LIN-USART interrupts
Table 20.5-1 Interrupt control bits and interrupt causes of LIN-USART
Reception/ Interrupt
transmission/ request
ICU flag bit
Reception RDRF
ORE
FRE
PE
LBD
Transmission TDRE
3 RBI, TBI
Bus Idle
Input Capture 2
ICPy
Unit
❍: Used
✕
: Unused
1
: Only available if ECCRn/SSM = 1
2
: For the Input Capture Unit number y refer to chapter 1.6 "Input Capture Unit source select for LIN-USART"
3
: It is not recommended to use bus idle interrupt with ESIR:AICD = 0, because in this case, as soon as reception activity
starts, this interrupt is cleared.
496
Flag Operation
Register mode
0 1 2 3
❍ ❍ ❍ ❍ receive data is
SSRn
❍ ❍ ❍ ❍ Overrun error
SSRn
❍ ❍ ❍ Framing error
SSRn 1
✕ ✕
❍
SSRn
1
✕ ✕ ✕
❍ LIN synch break
ESCRn
❍ ❍ ❍ ❍ TDRn empty
SSRn
❍ ❍ ❍ ❍ Neither transmission
ECCRn,
ESIRn
✕ ✕ ✕
❍ 1st falling edge of
2
ICSy
MB96300 Super Series Hardware Manual
Interrupt cause Interrupt
cause enable
SSRn:RIE
written to RDRn
Parity error
ESCRn:LBIE
detected
SSRn:TIE
ECCRn:BIE
nor reception
activity
ICSy:ICEy
LIN synch field
5th falling edge of
LIN synch field
How to clear the
Interrupt Request
bit
Receive data
is read
"1" is written to
clear rec. error
bit (SCRn: CRE)
"0" is written to
ESCRn: LBD
Write data to
TDRn
Write "0" to
ESIRn:RBI, write
data to TDRn
2 disable ICPy
temporarily
disable ICPy