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clock divider 1 out of the System clock 1 (CLKS1).
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System clock 2 (CLKS2)
The System clock 2 (CLKS2) is a second master clock which is never modulated. It feeds the clock divider
for the Peripheral Clock 2 (CLKP2) only.
Depending on the SC2S[1:0] (System Clock 2 Select) bits of the CKSR register, one of the following 4
clocks can be selected as the System clock 2: CLKRC (RC clock), CLKMC (Main clock), CLKPLL
(unmodulated PLL clock) or CLKSC (Sub clock).
The setting of these bits does not influence the clock mode of the CPU which is defined by SC1S[1:0] only.
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Peripheral clock 2 (CLKP2)
The Peripheral clock 2 (CLKP2) is the clock source for peripheral resources that never operate with a
modulated clock. It is stopped in Timer and Stop mode. It is generated by the programmable Peripheral
clock divider 2 out of the System clock 2 (CLKS2).
●
Peripheral clock 3 (CLKP3)
The Peripheral clock 3 (CLKP3) is an optional second clock source for peripherals that never operate with
a modulated clock and which need a different clock frequency than those connected to CLKP2. CLKP3 is
stopped in Timer and Stop mode and is generated by the programmable Peripheral Clock Divider 3 from
System clock 2 (CLKS2).
CLKP3 clock is not available for all devices. Please refer to Datasheet.
In case the USB function is used, CLKP3 needs to be set to 48MHz
■ Source Clock Timers
The Main clock, RC clock and the Sub clock oscillators feed dedicated source clock timers (Main Clock
Timer, RC Clock Timer and Sub Clock Timer) which are running independently of the selected System
clock, Bus clock and Peripheral clock.
CHAPTER 6 CLOCKS
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