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MB96300 Super Series Hardware Manual
Figure 11.2-2 Configuration of the Watchdog Timer Configuration Register (WDTC)
7
Address:
00040E
-
RSTP WTCS1 WTCS0 WTI3
H
-
R/W R/W R/W R/W
X
: undefined value
R/W
: Readable and writable
: Initial value
6
5
4
3
2
1
0
WTI2
WTI1 WTI0
R/W R/W R/W
bit3
WTI3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CHAPTER 11 WATCHDOG TIMER AND WATCHDOG RESET
Initial value
X 0 0 0 0 0 0 0
B
bit2
bit1
bit0
Watchdog Timer Interval selection bits
WTI2
WTI1
WTI0
9
0
0
0
2
/ CLKWT
10
0
0
1
2
/ CLKWT
11
0
1
0
2
/ CLKWT
12
0
1
1
2
/ CLKWT
13
1
0
0
2
/ CLKWT
14
1
0
1
2
/ CLKWT
15
1
1
0
2
/ CLKWT
16
1
1
1
2
/ CLKWT
17
0
0
0
2
/ CLKWT
18
0
0
1
2
/ CLKWT
19
0
1
0
2
/ CLKWT
20
0
1
1
2
/ CLKWT
21
1
0
0
2
/ CLKWT
22
1
0
1
2
/ CLKWT
23
1
1
0
2
/ CLKWT
24
1
1
1
2
/ CLKWT
bit5
bit4
WTCS1
WTCS0
Watchdog Timer Clock Selection bits
CLKWT = CLKRC (internal RC oscillation clock,
RC clock frequency can be changed during
0
0
Watchdog operation)
CLKWT = CLKRC (internal RC oscillation clock,
changing RC clock frequency during Watchdog
0
1
operation causes Watchdog reset)
1
0
CLKWT = CLKMC (Main oscillation clock)
1
1
CLKWT = CLKSC (Sub oscillation clock)
bit6
RSTP
Watchdog Reset at transition to Stop mode
0
No Watchdog Reset asserted at transition to Stop mode
1
Watchdog Reset asserted at transition to Stop mode
bit7
-
0
Always write "0" to this bit
(CLKWT is clock selected by
WTCS[1:0] bits)
Reserved
283
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