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MB96300 Super Series Hardware Manual
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Power reset
A power reset is generated when the power is turned on with a power on rise time as specified in the
datasheet (power-on reset) or when the low voltage detector detects that the power supply Vcc falls below a
certain value as specified in the LVL bits of the CILCR register (low voltage reset). Refer to the Datasheet
for the analog LVL levels. A power reset is internally prolonged by the Power reset extension circuit to a
minimum length of 700 RC clock cycles
The contents of internal RAM and all registers with initial value 'X' is undefined after a Power reset.
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External pin reset
An External pin reset is generated by a L level input to the external reset pin (RST pin). This signal is
internally prolonged by the External reset extension circuit to a minimum length of 700 RC clock cycles.
Because the external reset is asynchronous, it becomes active with little delay (some 10ns) after assertion,
disregarding whether the device is clocked or not.
The contents of internal RAM and all registers which are not reset (initial value 'X') is maintained except for
the 4 bytes at the address 7FFC-7FFF.
RST
Pin
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Clock stop detection reset
A Clock stop detection reset is generated upon a failure of the Main or Sub clock oscillator depending on the
current operation mode and the setting of the Reset Configuration Register (RCR). See section 8.6
"Operation of the Clock stop detection function and reset" for more details.
The contents of internal RAM memory and all registers which are not reset (initial value 'X') cannot be
guaranteed after a Clock stop detection reset.
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Software reset
A Software reset is an internal reset generated by writing "1" to the SRSTG bit of the Reset Configuration
Register (RCR).
The contents of internal RAM and all registers which are not reset (initial value 'X') is maintained.
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Watchdog timer reset
A Watchdog timer reset is generated when the watchdog timer is activated but not cleared within the defined
period as specified in the chapter CHAPTER 11 "WATCHDOG TIMER AND WATCHDOG RESET"
Figure 8.1-1 Block diagram of external reset pin
Pch
Nch
Input
buffer
CHAPTER 8 RESETS AND STARTUP
Noise Filter for
Reset
falling edge
Controller
global reset
to all MCU
modules
193
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