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CHAPTER 6 CLOCKS
■ Source clocks
The following clock signals are the clock sources of the F2MC-16FX MCU.
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RC clock (CLKRC)
The RC clock CLKRC is the output clock of the internal RC oscillator. The RC oscillator can generate two
different clock frequencies (2MHz and 100kHz nominal, see datasheet) which can be selected with the
RCFS (RC Clock Frequency Select) bit of the CKFCR register.
●
Main clock (CLKMC)
The Main clock CLKMC is the output clock of the main oscillation circuit. Either an external oscillator or
an external clock can be connected to the main oscillation circuit.
●
PLL clock (CLKPLL)
The PLL clock CLKPLL is obtained by multiplying the Main clock CLKMC with the internal PLL clock
multiplier circuit (PLL oscillation circuit). Multiplication rates from 1 to 32 are available.
This clock is only available when the Main clock CLKMC is active.
●
Sub clock (CLKSC)
The Sub clock CLKSC is the output clock of the sub oscillation circuit. Either an external oscillator or an
external clock can be connected to the sub oscillation circuit.
The Sub clock is not available for all F2MC-16FX MCUs.
■ Internally derived clocks
The following clock signals are internally generated out of the source clocks.
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Modulated PLL clock (CLKMOD)
The PLL clock CLKPLL can be modulated with the built-in clock modulator to reduce the electromagnetic
emission. The output clock of this clock modulator is called CLKMOD.
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System clock 1 (CLKS1)
The System clock 1 (CLKS1) is a master clock of the F2MC-16FX MCU. It feeds the clock divider for the
Bus clock (CLKB) and the Peripheral Clock 1 (CLKP1) and defines the clock mode of the CPU.
Depending on the SC1S[1:0] (System Clock 1 Select) bits of the CKSR register, one of the following 4
clocks can be selected as the System clock 1: CLKRC (RC clock), CLKMC (Main clock), CLKPLL/
CLKMOD (unmodulated or modulated PLL clock) or CLKSC (Sub clock).
●
Bus clock (CLKB)
The Bus clock CLKB is the clock source for the internal bus, the CPU, internal memories, DMA controller
and the external bus interface. It is stopped in all Standby modes (Sleep, Timer and Stop mode). It is
generated by the programmable Bus clock divider out of the System clock 1 (CLKS1).
●
Peripheral clock 1 (CLKP1)
The Peripheral clock 1 (CLKP1) is the clock source for all peripheral resources that can operate with a
modulated clock. It is stopped in Timer and Stop mode. It is generated by the programmable Peripheral
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