Notes On Using Flash Memory - Fujitsu MB96300 series Hardware Manual

33.8

Notes on using Flash Memory

This section contains notes on using flash memory.
■ Notes on using flash memory
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Compatibility to MBM29LV200TC
Please review the MBM29LV200TC data sheet in conjunction with this document.
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Input of a hardware reset (RST)
A hardware reset during writing causes the data being written to be undefined.
Resetting the device once execution of sector erase has begun will corrupt the data in the sector. In that
case, restart the erase on this sector and allow it to complete.
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Canceling of a software reset and watchdog timer reset
When the flash memory is being written to or erased with CPU access and if reset conditions occur while
the automatic algorithm is active, the CPU may run out of control. This occurs because these reset
conditions cause the automatic algorithm to continue without initializing the flash memory unit, possibly
preventing the flash memory unit from entering the read state when the CPU starts the sequence after the
reset has been deasserted. These reset conditions must be disabled during writing to or erasing of the flash
memory.
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Program access to flash memory
When the automatic algorithm is operating, read access to the flash memory at which the automatic
algorithm is active, is disabled.
Hence, make sure that the CPU is not executing code from a flash memory that is erased/written. If the
"main" flash memory is to be erased/written, make sure that code is executed only from the "satellite" flash
memory (if available) or from RAM. If the "satellite" flash memory is to be erased/written, make sure that
code is executed only from the "main" flash memory or from RAM.
For the same reason, make sure that the table base register (TBR) is not pointing to an interrupt vector table
located in flash memory to be erased or written to. Program TBR to point to an interrupt vector table in the
other flash memory (if available) or in RAM, or disable interrupts completely before starting the automatic
algorithm.
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Hold function
When the CPU accepts a hold request, the Write signal WE of the flash memory unit may be skewed,
causing erroneous writing or erasing due to an erroneous write. When the acceptance of a hold request is
enabled (HDE bit of EPCR set to 1), ensure that the WE bit of the control status register (FMCS) is 0.
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DMA
DMA can not be used to serve write and erase interrupts of the Flash memory.
CHAPTER 33 FLASH MEMORY
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