Fujitsu MB96300 series Hardware Manual page 184

CHAPTER 6 CLOCKS
X1/X1A
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RC clock stabilization interval
The RC clock stabilization time is fixed to 64 RC clock cycles. However after a Power reset or an External
reset (RST falling edge), an additional wait time of 700 RC clock cycle (Power reset) or 700 RC clock
cycles (External reset) is applied by the reset extension circuit (see section 8.3 Startup after Power and
External reset for more details).
●
Main clock stabilization interval
The Main clock stabilization time can be selected with the MCST[2:0] bits of the CKSSR register. 8
settings are possible as described in Table 6.2-3.
●
Sub clock stabilization interval
The Sub clock stabilization time can be selected with the SCST[1:0] bits of the CKSSR register. 4 settings
are possible as described in Table 6.2-3.
●
PLL clock stabilization interval
The PLL clock stabilization time can be selected with the PCST bit of the CKSSR register. 2 settings are
possible as described in Table 6.2-3.
176
Figure 6.5-1 Operation Immediately after Oscillation Starts
Oscillator-activated
oscillation time
Start of oscillation Stable oscillation
Oscillation stabilization Clock can be used
wait interval
...
Clock ready flag set
as System clock