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CHAPTER 6 CLOCKS
Figure 6.2-6 Configuration of the PLL Control Register (PLLCR)
Address:
15
14
000406
H
-
-
000407
H
-
-
X
: undefined value
R/W
: Readable and writable
: Initial value
164
13
12
11
10
9
8
-
-
PC3D3
PC3D2 PC3D1 PC3D0
-
-
R/W
R/W R/W R/W
bit4
PMS4
0
0
...
1
For devices that do support CLKP3
For devices that do not support CLKP3
7
6
5
4
3
2
VMS2 VMS1 VMS0 PMS4 PMS3
PMS2 PMS1 PMS0
R/W R/W R/W R/W R/W
R/W R/W R/W
bit3
bit2
bit1
bit0
PMS3
PMS2
PMS1
PMS0
0
0
0
0
0
0
0
1
...
...
...
...
1
1
1
1
bit7
bit6
bit5
VMS2
VMS1
VMS0
0
0
0
VCO Clock is CLKPLL multiplied by 2
0
0
1
VCO Clock is CLKPLL multiplied by 4
0
1
0
VCO Clock is CLKPLL multiplied by 6
0
1
1
VCO Clock is CLKPLL multiplied by 8
1
0
0
VCO Clock is CLKPLL multiplied by 10
1
0
1
VCO Clock is CLKPLL multiplied by 12
1
1
0
VCO Clock is CLKPLL multiplied by 14
1
1
1
VCO Clock is CLKPLL multiplied by 16
bit11
bit10
bit9
bit8
PC3D3
PC3D2
PC3D1
PC3D0
0
0
0
0
0
0
0
1
0
0
1
0
...
...
...
...
1
1
1
0
1
1
1
1
bit11 - bit8
-
X
Always write "0" to these bits
bit15 - bit12
-
0
Always write "0" to these bits
1
0
Initial value
X X X X 0 0 0 0 0 0 0 0 0 0 0 0
PLL clock Multiplier Select bits
CLKPLL is CLKMC (multiplied by 1)
CLKPLL is CLKMC multiplied by 2
CLKPLL is CLKMC multiplied by PMS[3:0]
CLKPLL is CLKMC multiplied by 32
VCO clock Multiplier Select bits
Peripheral Clock 3 Division select bits
CLKP3 is CLKS2 (divided by 1)
CLKP3 is CLKS2 divided by 2
CLKP3 is CLKS2 divided by 3
CLKP3 is CLKS2 divided by PC3D[3:0]
CLKP3 is CLKS2 divided by 15
CLKP3 is CLKS2 divided by 16
Reserved
Reserved
B
+ 1
B
+ 1
B
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