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CHAPTER 23 CLOCK OUTPUT FUNCTION
■ Clock Output Configuration Register (COCR)
15/7 14/6 13/5 12/4 11/3 10/2
Address:
COCR1: 000417
H
-
COCR0: 000416
H
-
R/W
: Readable and writable
: Initial value
632
Figure 23.2-1 Clock Output Configuration Register (COCR)
DIV2
DIV1
DIV0
SEL3
SEL2
SEL1
R/W
R/W R/W R/W
R/W R/W R/W
bit11/3
SEL3
*CLKP3 is not available for all devices. Please refer to the datasheet of your device.
MB96300 Super Series Hardware Manual
9/1
8/0
Initial value
X 0 0 0 0 0 0 0
SEL0
B
bit10/2
bit9/1
bit8/0
SEL2
SEL1
SEL0
0
0
0
0
No clock
0
0
0
1
CLKRC (RC clock)
0
0
1
0
CLKMC (Main clock)
0
0
1
1
CLKSC (Sub clock)
0
1
0
0
CLKPLL (PLL output clock)
0
1
0
1
CLKMOD (Modulated PLL clock)
0
1
1
0
CLKS1 (System clock 1)
0
1
1
1
CLKS2 (System clock 2)
1
0
0
0
CLKB (Bus clock)
1
0
0
1
CLKP1 (Peripheral clock 1)
1
0
1
0
CLKP2 (Peripheral clock 2)
1
0
1
1
CLKVCO (VCO clock of PLL)
1
1
0
0
CLKPLLFB (PLL feedback clock)
1
1
0
1
CLKP3 (Peripheral clock 3) *
1
1
1
0
reserved
1
1
1
1
reserved
bit14/6
bit13/5
bit12/4
DIV2
DIV1
DIV0
0
0
0
Output clock is not divided
0
0
1
Output clock is divided by 2
0
1
0
Output clock is divided by 4
0
1
1
Output clock is divided by 8
1
0
0
Output clock is divided by 16
1
0
1
Output clock is divided by 32
1
1
0
Output clock is divided by 64
1
1
1
Output clock is divided by 128
bit15/7
-
0
Always write "0" to this bit
Clock Select bits
Clock Division bits
Reserved
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