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MB96300 Super Series Hardware Manual
Table 8.5-2 Function Description of the Bits of the Reset Cause and Clock Status Register (RCCSR) (1/2)
Bit name
bit 8
PRST:
Power Reset
cause bit
bit 9
ERST:
External Reset
cause bit
bit 10
MCRST:
Main Clock stop
detection Reset
cause bit
bit 11
SCRST:
Sub Clock stop
detection Reset
cause bit
bit 12
SRST:
Software Reset
cause bit
bit 13
WRST:
Watchdog timer
Reset cause bit
• This bit indicates if a Power reset was generated.
• After Power-on, this bit is set to "1".
• This bit can only be cleared by a read access to RCCSRC at address 00040B
• This bit is set to "1" if a Power reset was generated. Possible reset causes are:
1. Power-on event: The power was turned on according to the profile described in the
datasheet.
2. Low voltage event: The low voltage reset function was enabled and the power supply
dropped below a value described in the datasheet.
• This bit indicates if an External reset was generated.
• This bit is set to "1" if an External reset was generated by asserting RST to "0".
• After a Power reset, this bit is also set to '1'.
• This bit can only be cleared by a read access to RCCSRC at address 00040B
• This bit indicates if a Main Clock stop detection reset was generated.
• After a Power reset, this bit is not initialized.
• This bit can only be cleared by a read access to RCCSRC at address 00040B
• This bit is set to "1" if a Main Clock stop detection reset was generated. Possible reset
causes are:
1. A missing Main clock was detected while the Main or the PLL clock was selected for
the System clock CLKS1 or CLKS2 or the Watchdog timer.
2. "0" was written to the enable bit of the RC clock (CKSR: RCE) although the Clock
stop detection reset was enabled.
• This bit indicates if a Sub Clock stop detection reset was generated.
• After a Power reset, this bit is not initialized.
• This bit can only be cleared by a read access to RCCSRC at address 00040B
• This bit is set to "1" if a Sub Clock stop detection reset was generated. Possible reset
causes are:
1. A missing Sub clock was detected while the Sub clock was selected for the System
clock CLKS1 or CLKS2 or the Watchdog timer.
2. "0" was written to the enable bit of the RC clock (CKSR: RCE) although the Clock
stop detection reset was enabled.
• This bit indicates if a Software reset was generated.
• After a Power reset, this bit is not initialized.
• This bit can only be cleared by a read access to RCCSRC at address 00040B
• This bit is set to "1" if a Software reset was generated by writing "1" to the RCR:
SRSTG bit.
• This bit indicates if a Watchdog timer reset was generated.
• After a Power reset, this bit is not initialized.
• This bit can only be cleared by a read access to RCCSRC at address 00040B
• This bit is set to "1" if a Watchdog timer reset was generated. Possible reset causes are:
1. The Watchdog timer was activated but not cleared within the selected interval.
2. An illegal value was written to the Watchdog Timer Clear Pattern register.
3. "0" was written to the enable bit of the clock which is used as source clock of the
Watchdog timer (CKSR: RCE, MCE or SCE) to disable this clock.
4. RC clock frequency was changed although Watchdog Timer Clock Selection bits
were set to "01" (changing RC clock frequency not allowed).
5. Transition to Stop mode was requested although the WDTC:RSTP bit was set to '1'.
CHAPTER 8 RESETS AND STARTUP
Function
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